Commit 8ff2eb62 authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: frequency: ad9523: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: cd1678f9 ("iio: frequency: New driver for AD9523 SPI Low Jitter Clock Generator")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-66-jic23@kernel.org
parent b9ac08b3

drivers/iio/frequency/ad9523.c

+3 −3
Original line number Diff line number Diff line
@@ -287,13 +287,13 @@ struct ad9523_state { 
	struct mutex		lock;



	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * transfer buffers to live in their own cache lines.

	 * DMA (thus cache coherency maintenance) may require that

	 * transfer buffers live in their own cache lines.

	 */

	union {

		__be32 d32;

		u8 d8[4];

	} data[2] ____cacheline_aligned;

	} data[2] __aligned(IIO_DMA_MINALIGN);

};



static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr)