perf vendors events arm64: Arm Cortex-A510 (3935c302) · Commits · jan.koester / Linux

tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json

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		[
		{
		"ArchStdEvent": "BR_MIS_PRED"
		},
		{
		"ArchStdEvent": "BR_PRED"
		},
		{
		"ArchStdEvent": "BR_IMMED_SPEC"
		},
		{
		"ArchStdEvent": "BR_RETURN_SPEC"
		},
		{
		"ArchStdEvent": "BR_INDIRECT_SPEC"
		},
		{
		"PublicDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off",
		"EventCode": "0xC9",
		"EventName": "BR_COND_PRED",
		"BriefDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off"
		},
		{
		"PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off",
		"EventCode": "0xCA",
		"EventName": "BR_INDIRECT_MIS_PRED",
		"BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off"
		},
		{
		"PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
		"EventCode": "0xCB",
		"EventName": "BR_INDIRECT_ADDR_MIS_PRED",
		"BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
		},
		{
		"PublicDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count",
		"EventCode": "0xCC",
		"EventName": "BR_COND_MIS_PRED",
		"BriefDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count"
		},
		{
		"PublicDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
		"EventCode": "0xCD",
		"EventName": "BR_INDIRECT_ADDR_PRED",
		"BriefDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
		},
		{
		"PublicDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
		"EventCode": "0xCE",
		"EventName": "BR_RETURN_ADDR_PRED",
		"BriefDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
		},
		{
		"PublicDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
		"EventCode": "0xCF",
		"EventName": "BR_RETURN_ADDR_MIS_PRED",
		"BriefDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
		}
		]

tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json

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		[
		{
		"ArchStdEvent": "CPU_CYCLES"
		},
		{
		"ArchStdEvent": "BUS_ACCESS"
		},
		{
		"ArchStdEvent": "BUS_CYCLES"
		},
		{
		"ArchStdEvent": "BUS_ACCESS_RD"
		},
		{
		"ArchStdEvent": "BUS_ACCESS_WR"
		}
		]

tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json

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		[
		{
		"ArchStdEvent": "L1I_CACHE_REFILL"
		},
		{
		"ArchStdEvent": "L1I_TLB_REFILL"
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL"
		},
		{
		"ArchStdEvent": "L1D_CACHE"
		},
		{
		"ArchStdEvent": "L1D_TLB_REFILL"
		},
		{
		"ArchStdEvent": "L1I_CACHE"
		},
		{
		"ArchStdEvent": "L1D_CACHE_WB"
		},
		{
		"ArchStdEvent": "L2D_CACHE"
		},
		{
		"ArchStdEvent": "L2D_CACHE_REFILL"
		},
		{
		"ArchStdEvent": "L2D_CACHE_WB"
		},
		{
		"ArchStdEvent": "L2D_CACHE_ALLOCATE"
		},
		{
		"ArchStdEvent": "L1D_TLB"
		},
		{
		"ArchStdEvent": "L1I_TLB"
		},
		{
		"ArchStdEvent": "L3D_CACHE"
		},
		{
		"ArchStdEvent": "L2D_TLB_REFILL"
		},
		{
		"ArchStdEvent": "L2D_TLB"
		},
		{
		"ArchStdEvent": "DTLB_WALK"
		},
		{
		"ArchStdEvent": "ITLB_WALK"
		},
		{
		"ArchStdEvent": "LL_CACHE_RD"
		},
		{
		"ArchStdEvent": "LL_CACHE_MISS_RD"
		},
		{
		"ArchStdEvent": "L1D_CACHE_LMISS_RD"
		},
		{
		"ArchStdEvent": "L1D_CACHE_RD"
		},
		{
		"ArchStdEvent": "L1D_CACHE_WR"
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL_RD"
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL_WR"
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
		},
		{
		"ArchStdEvent": "L2D_CACHE_RD"
		},
		{
		"ArchStdEvent": "L2D_CACHE_WR"
		},
		{
		"ArchStdEvent": "L2D_CACHE_REFILL_RD"
		},
		{
		"ArchStdEvent": "L2D_CACHE_REFILL_WR"
		},
		{
		"ArchStdEvent": "L3D_CACHE_RD"
		},
		{
		"ArchStdEvent": "L3D_CACHE_REFILL_RD"
		},
		{
		"PublicDescription": "L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented",
		"EventCode": "0xC1",
		"EventName": "L2D_CACHE_REFILL_PREFETCH",
		"BriefDescription": "L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented"
		},
		{
		"PublicDescription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache",
		"EventCode": "0xC2",
		"EventName": "L1D_CACHE_REFILL_PREFETCH",
		"BriefDescription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache"
		},
		{
		"PublicDescription": "L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache",
		"EventCode": "0xC3",
		"EventName": "L2D_WS_MODE",
		"BriefDescription": "L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache"
		},
		{
		"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode",
		"EventCode": "0xC4",
		"EventName": "L1D_WS_MODE_ENTRY",
		"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode"
		},
		{
		"PublicDescription": "L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache",
		"EventCode": "0xC5",
		"EventName": "L1D_WS_MODE",
		"BriefDescription": "L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache"
		},
		{
		"PublicDescription": "L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache",
		"EventCode": "0xC7",
		"EventName": "L3D_WS_MODE",
		"BriefDescription": "L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache"
		},
		{
		"PublicDescription": "Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache",
		"EventCode": "0xC8",
		"EventName": "LL_WS_MODE",
		"BriefDescription": "Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache"
		},
		{
		"PublicDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled",
		"EventCode": "0xD0",
		"EventName": "L2D_WALK_TLB",
		"BriefDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled"
		},
		{
		"PublicDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled",
		"EventCode": "0xD1",
		"EventName": "L2D_WALK_TLB_REFILL",
		"BriefDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled"
		},
		{
		"PublicDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count",
		"EventCode": "0xD4",
		"EventName": "L2D_S2_TLB",
		"BriefDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count"
		},
		{
		"PublicDescription": "L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count",
		"EventCode": "0xD5",
		"EventName": "L2D_S2_TLB_REFILL",
		"BriefDescription": "L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count"
		},
		{
		"PublicDescription": "L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request",
		"EventCode": "0xD6",
		"EventName": "L2D_CACHE_STASH_DROPPED",
		"BriefDescription": "L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request"
		},
		{
		"ArchStdEvent": "L1I_CACHE_LMISS"
		},
		{
		"ArchStdEvent": "L2D_CACHE_LMISS_RD"
		},
		{
		"ArchStdEvent": "L3D_CACHE_LMISS_RD"
		}
		]

tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json

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		[
		{
		"ArchStdEvent": "EXC_TAKEN"
		},
		{
		"ArchStdEvent": "MEMORY_ERROR"
		},
		{
		"ArchStdEvent": "EXC_IRQ"
		},
		{
		"ArchStdEvent": "EXC_FIQ"
		}
		]

tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json

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		[
		{
		"ArchStdEvent": "LD_RETIRED"
		},
		{
		"ArchStdEvent": "ST_RETIRED"
		},
		{
		"ArchStdEvent": "INST_RETIRED"
		},
		{
		"ArchStdEvent": "EXC_RETURN"
		},
		{
		"ArchStdEvent": "CID_WRITE_RETIRED"
		},
		{
		"ArchStdEvent": "PC_WRITE_RETIRED"
		},
		{
		"ArchStdEvent": "BR_IMMED_RETIRED"
		},
		{
		"ArchStdEvent": "BR_RETURN_RETIRED"
		},
		{
		"ArchStdEvent": "INST_SPEC"
		},
		{
		"ArchStdEvent": "TTBR_WRITE_RETIRED"
		},
		{
		"ArchStdEvent": "BR_RETIRED"
		},
		{
		"ArchStdEvent": "BR_MIS_PRED_RETIRED"
		},
		{
		"ArchStdEvent": "OP_RETIRED"
		},
		{
		"ArchStdEvent": "OP_SPEC"
		},
		{
		"ArchStdEvent": "LD_SPEC"
		},
		{
		"ArchStdEvent": "ST_SPEC"
		},
		{
		"ArchStdEvent": "LDST_SPEC"
		},
		{
		"ArchStdEvent": "DP_SPEC"
		},
		{
		"ArchStdEvent": "ASE_SPEC"
		},
		{
		"ArchStdEvent": "VFP_SPEC"
		},
		{
		"ArchStdEvent": "PC_WRITE_SPEC"
		},
		{
		"ArchStdEvent": "CRYPTO_SPEC"
		},
		{
		"ArchStdEvent": "SVE_INST_RETIRED"
		},
		{
		"ArchStdEvent": "SVE_INST_SPEC"
		},
		{
		"ArchStdEvent": "FP_HP_SPEC"
		},
		{
		"ArchStdEvent": "FP_SP_SPEC"
		},
		{
		"ArchStdEvent": "FP_DP_SPEC"
		},
		{
		"ArchStdEvent": "ASE_SVE_INT8_SPEC"
		},
		{
		"ArchStdEvent": "ASE_SVE_INT16_SPEC"
		},
		{
		"ArchStdEvent": "ASE_SVE_INT32_SPEC"
		},
		{
		"ArchStdEvent": "ASE_SVE_INT64_SPEC"
		}
		]