Commit 40efe139 authored by Sameer Pujar's avatar Sameer Pujar Committed by Thierry Reding
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dt-bindings: Add Tegra234 APE support 



Add clocks, power-domain and memory bindings to support APE subsystem
on Tegra234.

Signed-off-by: default avatarSameer Pujar <spujar@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 38eb21a5

include/dt-bindings/clock/tegra234-clock.h

+73 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */

/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */



#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H

#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
@@ -9,6 +9,26 @@ 
 * @defgroup bpmp_clock_ids Clock ID's

 * @{

 */

/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */

#define TEGRA234_CLK_AHUB			4U

/** @brief output of gate CLK_ENB_APB2APE */

#define TEGRA234_CLK_APB2APE			5U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */

#define TEGRA234_CLK_APE			6U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */

#define TEGRA234_CLK_AUD_MCLK			7U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */

#define TEGRA234_CLK_DMIC1			15U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */

#define TEGRA234_CLK_DMIC2			16U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */

#define TEGRA234_CLK_DMIC3			17U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */

#define TEGRA234_CLK_DMIC4			18U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */

#define TEGRA234_CLK_DSPK1			29U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */

#define TEGRA234_CLK_DSPK2			30U

/**

 * @brief controls the EMC clock frequency.

 * @details Doing a clk_set_rate on this clock will select the
@@ -36,8 +56,36 @@ 
#define TEGRA234_CLK_I2C8			54U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */

#define TEGRA234_CLK_I2C9			55U

/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */

#define TEGRA234_CLK_I2S1			56U

/** @brief clock recovered from I2S1 input */

#define TEGRA234_CLK_I2S1_SYNC_INPUT		57U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */

#define TEGRA234_CLK_I2S2			58U

/** @brief clock recovered from I2S2 input */

#define TEGRA234_CLK_I2S2_SYNC_INPUT		59U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */

#define TEGRA234_CLK_I2S3			60U

/** @brief clock recovered from I2S3 input */

#define TEGRA234_CLK_I2S3_SYNC_INPUT		61U

/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */

#define TEGRA234_CLK_I2S4			62U

/** @brief clock recovered from I2S4 input */

#define TEGRA234_CLK_I2S4_SYNC_INPUT		63U

/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */

#define TEGRA234_CLK_I2S5			64U

/** @brief clock recovered from I2S5 input */

#define TEGRA234_CLK_I2S5_SYNC_INPUT		65U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */

#define TEGRA234_CLK_I2S6			66U

/** @brief clock recovered from I2S6 input */

#define TEGRA234_CLK_I2S6_SYNC_INPUT		67U

/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */

#define TEGRA234_CLK_PLLA			93U

/** @brief PLLP clk output */

#define TEGRA234_CLK_PLLP_OUT0			102U

/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */

#define TEGRA234_CLK_PLLA_OUT0			104U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */

#define TEGRA234_CLK_PWM1			105U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
@@ -56,6 +104,30 @@ 
#define TEGRA234_CLK_PWM8			112U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */

#define TEGRA234_CLK_SDMMC4			123U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */

#define TEGRA234_CLK_SYNC_DMIC1			139U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */

#define TEGRA234_CLK_SYNC_DMIC2			140U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */

#define TEGRA234_CLK_SYNC_DMIC3			141U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */

#define TEGRA234_CLK_SYNC_DMIC4			142U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */

#define TEGRA234_CLK_SYNC_DSPK1			143U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */

#define TEGRA234_CLK_SYNC_DSPK2			144U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */

#define TEGRA234_CLK_SYNC_I2S1			145U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */

#define TEGRA234_CLK_SYNC_I2S2			146U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */

#define TEGRA234_CLK_SYNC_I2S3			147U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */

#define TEGRA234_CLK_SYNC_I2S4			148U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */

#define TEGRA234_CLK_SYNC_I2S5			149U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */

#define TEGRA234_CLK_SYNC_I2S6			150U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */

#define TEGRA234_CLK_UARTA			155U

/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */

include/dt-bindings/memory/tegra234-mc.h

+7 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */



#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H

#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
@@ -7,6 +8,8 @@ 
#define TEGRA234_SID_INVALID		0x00

#define TEGRA234_SID_PASSTHROUGH	0x7f



/* NISO0 stream IDs */

#define TEGRA234_SID_APE	0x02



/* NISO1 stream IDs */

#define TEGRA234_SID_SDMMC4	0x02
@@ -28,5 +31,9 @@ 
#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95

/* BPMPDMA write client */

#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96

/* APEDMA read client */

#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f

/* APEDMA write client */

#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0



#endif

include/dt-bindings/power/tegra234-powergate.h

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+9 −0
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/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved. */



#ifndef __ABI_MACH_T234_POWERGATE_T234_H_

#define __ABI_MACH_T234_POWERGATE_T234_H_



#define TEGRA234_POWER_DOMAIN_AUD	2U



#endif