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Commit 44991eb4 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Sebastian Hesselbarth
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ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles 



For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 7171511e
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