Commit 4768349e authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Pass all structs in display_rq_dlg_helpers by pointer 



Passing structs adds a lot of overhead. We don't ever want to pass
anything bigger than primitives by value.

This patch fixes these Coverity IDs:
Addresses-Coverity-ID: 1423868: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423870: ("Big parameter passed by value")

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Cc: Nick Desaulniers <ndesaulniers@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: amd-gfx@lists.freedesktop.org
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Cc: Arnd Bergmann <arnd@kernel.org>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Xinhui Pan <Xinhui.Pan@amd.com>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: llvm@lists.linux.dev
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Build-tested-by: default avatarNathan Chancellor <nathan@kernel.org>
Reviewed-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 22667e6e

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

+16 −16
Original line number Diff line number Diff line
@@ -164,26 +164,26 @@ static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_si 


static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,

		display_data_rq_regs_st *rq_regs,

		const display_data_rq_sizing_params_st rq_sizing)

		const display_data_rq_sizing_params_st *rq_sizing)

{

	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);

	print__data_rq_sizing_params_st(mode_lib, rq_sizing);



	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;

	rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10;



	if (rq_sizing.min_chunk_bytes == 0)

	if (rq_sizing->min_chunk_bytes == 0)

		rq_regs->min_chunk_size = 0;

	else

		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;

		rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1;



	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;

	if (rq_sizing.min_meta_chunk_bytes == 0)

	rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10;

	if (rq_sizing->min_meta_chunk_bytes == 0)

		rq_regs->min_meta_chunk_size = 0;

	else

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1;



	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;

	rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6;

}



static void extract_rq_regs(struct display_mode_lib *mode_lib,
@@ -193,13 +193,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, 
	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;

	unsigned int detile_buf_plane1_addr = 0;



	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);

	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l);



	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),

			1) - 3;



	if (rq_param.yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),

				1) - 3;

	}
@@ -763,7 +763,7 @@ static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 


	// calculate how to split the det buffer space between luma and chroma

	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);

	print__rq_params_st(mode_lib, *rq_param);

	print__rq_params_st(mode_lib, rq_param);

}



void dml20_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
@@ -776,7 +776,7 @@ void dml20_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 
	dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src);

	extract_rq_regs(mode_lib, rq_regs, rq_param);



	print__rq_regs_st(mode_lib, *rq_regs);

	print__rq_regs_st(mode_lib, rq_regs);

}



// Note: currently taken in as is.
@@ -1542,8 +1542,8 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;

	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));



	print__ttu_regs_st(mode_lib, *disp_ttu_regs);

	print__dlg_regs_st(mode_lib, *disp_dlg_regs);

	print__ttu_regs_st(mode_lib, disp_ttu_regs);

	print__dlg_regs_st(mode_lib, disp_dlg_regs);

}



void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
@@ -1579,7 +1579,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 
	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency

			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated



	print__dlg_sys_params_st(mode_lib, dlg_sys_param);

	print__dlg_sys_params_st(mode_lib, &dlg_sys_param);



	// system parameter calculation done

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

+16 −16
Original line number Diff line number Diff line
@@ -164,26 +164,26 @@ static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_si 


static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,

		display_data_rq_regs_st *rq_regs,

		const display_data_rq_sizing_params_st rq_sizing)

		const display_data_rq_sizing_params_st *rq_sizing)

{

	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);

	print__data_rq_sizing_params_st(mode_lib, rq_sizing);



	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;

	rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10;



	if (rq_sizing.min_chunk_bytes == 0)

	if (rq_sizing->min_chunk_bytes == 0)

		rq_regs->min_chunk_size = 0;

	else

		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;

		rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1;



	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;

	if (rq_sizing.min_meta_chunk_bytes == 0)

	rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10;

	if (rq_sizing->min_meta_chunk_bytes == 0)

		rq_regs->min_meta_chunk_size = 0;

	else

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1;



	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;

	rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6;

}



static void extract_rq_regs(struct display_mode_lib *mode_lib,
@@ -193,13 +193,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, 
	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;

	unsigned int detile_buf_plane1_addr = 0;



	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);

	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l);



	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),

			1) - 3;



	if (rq_param.yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),

				1) - 3;

	}
@@ -763,7 +763,7 @@ static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 


	// calculate how to split the det buffer space between luma and chroma

	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);

	print__rq_params_st(mode_lib, *rq_param);

	print__rq_params_st(mode_lib, rq_param);

}



void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
@@ -776,7 +776,7 @@ void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 
	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src);

	extract_rq_regs(mode_lib, rq_regs, rq_param);



	print__rq_regs_st(mode_lib, *rq_regs);

	print__rq_regs_st(mode_lib, rq_regs);

}



// Note: currently taken in as is.
@@ -1543,8 +1543,8 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;

	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));



	print__ttu_regs_st(mode_lib, *disp_ttu_regs);

	print__dlg_regs_st(mode_lib, *disp_dlg_regs);

	print__ttu_regs_st(mode_lib, disp_ttu_regs);

	print__dlg_regs_st(mode_lib, disp_dlg_regs);

}



void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
@@ -1580,7 +1580,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 
	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency

			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated



	print__dlg_sys_params_st(mode_lib, dlg_sys_param);

	print__dlg_sys_params_st(mode_lib, &dlg_sys_param);



	// system parameter calculation done

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

+16 −16
Original line number Diff line number Diff line
@@ -141,26 +141,26 @@ static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_si 
static void extract_rq_sizing_regs(

		struct display_mode_lib *mode_lib,

		display_data_rq_regs_st *rq_regs,

		const display_data_rq_sizing_params_st rq_sizing)

		const display_data_rq_sizing_params_st *rq_sizing)

{

	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);

	print__data_rq_sizing_params_st(mode_lib, rq_sizing);



	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;

	rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10;



	if (rq_sizing.min_chunk_bytes == 0)

	if (rq_sizing->min_chunk_bytes == 0)

		rq_regs->min_chunk_size = 0;

	else

		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;

		rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1;



	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;

	if (rq_sizing.min_meta_chunk_bytes == 0)

	rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10;

	if (rq_sizing->min_meta_chunk_bytes == 0)

		rq_regs->min_meta_chunk_size = 0;

	else

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1;



	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;

	rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6;

}



static void extract_rq_regs(
@@ -171,14 +171,14 @@ static void extract_rq_regs( 
	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;

	unsigned int detile_buf_plane1_addr = 0;



	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);

	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l);



	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(

			dml_log2(rq_param.dlg.rq_l.dpte_row_height),

			1) - 3;



	if (rq_param.yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(

				dml_log2(rq_param.dlg.rq_c.dpte_row_height),

				1) - 3;
@@ -807,7 +807,7 @@ static void dml_rq_dlg_get_rq_params( 


	// calculate how to split the det buffer space between luma and chroma

	handle_det_buf_split(mode_lib, rq_param, pipe_param->src);

	print__rq_params_st(mode_lib, *rq_param);

	print__rq_params_st(mode_lib, rq_param);

}



void dml21_rq_dlg_get_rq_reg(
@@ -821,7 +821,7 @@ void dml21_rq_dlg_get_rq_reg( 
	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);

	extract_rq_regs(mode_lib, rq_regs, rq_param);



	print__rq_regs_st(mode_lib, *rq_regs);

	print__rq_regs_st(mode_lib, rq_regs);

}



// Note: currently taken in as is.
@@ -1650,8 +1650,8 @@ static void dml_rq_dlg_get_dlg_params( 
	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;

	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));



	print__ttu_regs_st(mode_lib, *disp_ttu_regs);

	print__dlg_regs_st(mode_lib, *disp_dlg_regs);

	print__ttu_regs_st(mode_lib, disp_ttu_regs);

	print__dlg_regs_st(mode_lib, disp_dlg_regs);

}



void dml21_rq_dlg_get_dlg_reg(
@@ -1691,7 +1691,7 @@ void dml21_rq_dlg_get_dlg_reg( 
	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency

			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated



	print__dlg_sys_params_st(mode_lib, dlg_sys_param);

	print__dlg_sys_params_st(mode_lib, &dlg_sys_param);



	// system parameter calculation done

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

+16 −16
Original line number Diff line number Diff line
@@ -89,26 +89,26 @@ static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_si 


static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,

	display_data_rq_regs_st *rq_regs,

	const display_data_rq_sizing_params_st rq_sizing)

	const display_data_rq_sizing_params_st *rq_sizing)

{

	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);

	print__data_rq_sizing_params_st(mode_lib, rq_sizing);



	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;

	rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10;



	if (rq_sizing.min_chunk_bytes == 0)

	if (rq_sizing->min_chunk_bytes == 0)

		rq_regs->min_chunk_size = 0;

	else

		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;

		rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1;



	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;

	if (rq_sizing.min_meta_chunk_bytes == 0)

	rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10;

	if (rq_sizing->min_meta_chunk_bytes == 0)

		rq_regs->min_meta_chunk_size = 0;

	else

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1;



	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;

	rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6;

}



static void extract_rq_regs(struct display_mode_lib *mode_lib,
@@ -118,13 +118,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, 
	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;

	unsigned int detile_buf_plane1_addr = 0;



	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);

	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l);



	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),

		1) - 3;



	if (rq_param.yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),

			1) - 3;

	}
@@ -872,7 +872,7 @@ static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 


	// calculate how to split the det buffer space between luma and chroma

	handle_det_buf_split(mode_lib, rq_param, pipe_param->src);

	print__rq_params_st(mode_lib, *rq_param);

	print__rq_params_st(mode_lib, rq_param);

}



void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
@@ -885,7 +885,7 @@ void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 
	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);

	extract_rq_regs(mode_lib, rq_regs, rq_param);



	print__rq_regs_st(mode_lib, *rq_regs);

	print__rq_regs_st(mode_lib, rq_regs);

}



static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
@@ -1824,8 +1824,8 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;

	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));



	print__ttu_regs_st(mode_lib, *disp_ttu_regs);

	print__dlg_regs_st(mode_lib, *disp_dlg_regs);

	print__ttu_regs_st(mode_lib, disp_ttu_regs);

	print__dlg_regs_st(mode_lib, disp_dlg_regs);

}



void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
@@ -1861,7 +1861,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 
	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency

		/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated



	print__dlg_sys_params_st(mode_lib, dlg_sys_param);

	print__dlg_sys_params_st(mode_lib, &dlg_sys_param);



	// system parameter calculation done

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

+16 −16
Original line number Diff line number Diff line
@@ -175,25 +175,25 @@ static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_si 
		return (4 * 1024);

}



static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st rq_sizing)

static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st *rq_sizing)

{

	print__data_rq_sizing_params_st(mode_lib, rq_sizing);



	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;

	rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10;



	if (rq_sizing.min_chunk_bytes == 0)

	if (rq_sizing->min_chunk_bytes == 0)

		rq_regs->min_chunk_size = 0;

	else

		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;

		rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1;



	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;

	if (rq_sizing.min_meta_chunk_bytes == 0)

	rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10;

	if (rq_sizing->min_meta_chunk_bytes == 0)

		rq_regs->min_meta_chunk_size = 0;

	else

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;

		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1;



	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;

	rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6;

	rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6;

}



static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st rq_param)
@@ -201,12 +201,12 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s 
	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;

	unsigned int detile_buf_plane1_addr = 0;



	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);

	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l);



	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 1) - 3;



	if (rq_param.yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 1) - 3;

	}
@@ -850,7 +850,7 @@ static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_ 


	// calculate how to split the det buffer space between luma and chroma

	handle_det_buf_split(mode_lib, rq_param, pipe_param->src);

	print__rq_params_st(mode_lib, *rq_param);

	print__rq_params_st(mode_lib, rq_param);

}



void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st *pipe_param)
@@ -861,7 +861,7 @@ void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_ 
	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);

	extract_rq_regs(mode_lib, rq_regs, rq_param);



	print__rq_regs_st(mode_lib, *rq_regs);

	print__rq_regs_st(mode_lib, rq_regs);

}



static void calculate_ttu_cursor(
@@ -1669,8 +1669,8 @@ static void dml_rq_dlg_get_dlg_params( 
	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;

	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));



	print__ttu_regs_st(mode_lib, *disp_ttu_regs);

	print__dlg_regs_st(mode_lib, *disp_dlg_regs);

	print__ttu_regs_st(mode_lib, disp_ttu_regs);

	print__dlg_regs_st(mode_lib, disp_dlg_regs);

}



void dml31_rq_dlg_get_dlg_reg(
@@ -1699,7 +1699,7 @@ void dml31_rq_dlg_get_dlg_reg( 
	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes);

	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes);



	print__dlg_sys_params_st(mode_lib, dlg_sys_param);

	print__dlg_sys_params_st(mode_lib, &dlg_sys_param);



	// system parameter calculation done