Commit 49c19337 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
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ARM: dts: qcom: align SDHCI clocks with DT schema 



The DT schema expects clocks iface-core order.  No functional change.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-6-krzysztof.kozlowski@linaro.org
parent 5eb82ddb

arch/arm/boot/dts/qcom-apq8084.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -425,10 +425,10 @@ mmc@f9824900 { 
			reg-names = "hc", "core";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			status = "disabled";

		};
@@ -438,10 +438,10 @@ mmc@f98a4900 { 
			reg-names = "hc", "core";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,

				 <&gcc GCC_SDCC2_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			status = "disabled";

		};

arch/arm/boot/dts/qcom-ipq4019.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -228,9 +228,9 @@ sdhci: mmc@7824900 { 
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			bus-width = <8>;

			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_DCD_XO_CLK>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			status = "disabled";

		};

arch/arm/boot/dts/qcom-msm8226.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -134,10 +134,10 @@ sdhc_1: mmc@f9824900 { 
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			pinctrl-names = "default";

			pinctrl-0 = <&sdhc1_default_state>;

			status = "disabled";
@@ -150,10 +150,10 @@ sdhc_2: mmc@f98a4900 { 
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,

				 <&gcc GCC_SDCC2_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			pinctrl-names = "default";

			pinctrl-0 = <&sdhc2_default_state>;

			status = "disabled";
@@ -166,10 +166,10 @@ sdhc_3: mmc@f9864900 { 
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC3_APPS_CLK>,

				 <&gcc GCC_SDCC3_AHB_CLK>,

			clocks = <&gcc GCC_SDCC3_AHB_CLK>,

				 <&gcc GCC_SDCC3_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			pinctrl-names = "default";

			pinctrl-0 = <&sdhc3_default_state>;

			status = "disabled";

arch/arm/boot/dts/qcom-msm8974.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -443,10 +443,10 @@ sdhc_1: mmc@f9824900 { 
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			bus-width = <8>;

			non-removable;
@@ -460,10 +460,10 @@ sdhc_3: mmc@f9864900 { 
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC3_APPS_CLK>,

				 <&gcc GCC_SDCC3_AHB_CLK>,

			clocks = <&gcc GCC_SDCC3_AHB_CLK>,

				 <&gcc GCC_SDCC3_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			bus-width = <4>;



			#address-cells = <1>;
@@ -479,10 +479,10 @@ sdhc_2: mmc@f98a4900 { 
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,

				 <&gcc GCC_SDCC2_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			bus-width = <4>;



			#address-cells = <1>;

arch/arm/boot/dts/qcom-msm8974pro.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -10,10 +10,10 @@ &gpu { 
};



&sdhc_1 {

	clocks = <&gcc GCC_SDCC1_APPS_CLK>,

		 <&gcc GCC_SDCC1_AHB_CLK>,

	clocks = <&gcc GCC_SDCC1_AHB_CLK>,

		 <&gcc GCC_SDCC1_APPS_CLK>,

		 <&xo_board>,

		 <&gcc GCC_SDCC1_CDCCAL_FF_CLK>,

		 <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>;

	clock-names = "core", "iface", "xo", "cal", "sleep";

	clock-names = "iface", "core", "xo", "cal", "sleep";

};