Commit 4c9b2507 authored by Richard Schleich's avatar Richard Schleich Committed by Florian Fainelli
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ARM: dts: bcm2835/6: Add the missing L1/L2 cache information 



This patch adds the cache info for the BCM2835 and BCM2836.
However, while testing I noticed that this is
not implemented for ARMv6/7.
Basically arch/arm/kernel/cacheinfo.c and other topology
related code is missing.
Since the work is already done and this has no negative effects,
I am submitting it for future/documentation purposes.

Signed-off-by: default avatarRichard Schleich <rs@noreya.tech>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 618682b3

arch/arm/boot/dts/bcm2835.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -14,6 +14,23 @@ cpu@0 { 
			device_type = "cpu";

			compatible = "arm,arm1176jzf-s";

			reg = <0x0>;

			/* Source for d/i-cache-line-size and d/i-cache-sets

			 * https://developer.arm.com/documentation/ddi0301

			 * /h/level-one-memory-system/cache-organization?lang=en

			 *

			 * Source for d/i-cache-size

			 * https://forums.raspberrypi.com/viewtopic.php?t=98428

			 *

			 * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU

			 * It can be shared with the CPU through fw settings,

			 * but this is not recommended.

			 */

			d-cache-size = <0x4000>;

			d-cache-line-size = <16>;

			d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set

			i-cache-size = <0x4000>;

			i-cache-line-size = <16>;

			i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set

		};

	};

arch/arm/boot/dts/bcm2836.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -41,11 +41,26 @@ cpus: cpus { 
		#size-cells = <0>;

		enable-method = "brcm,bcm2836-smp";



		/* Source for d/i-cache-line-size and d/i-cache-sets

		 * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System

		 * /About-the-L1-memory-system?lang=en

		 *

		 * Source for d/i-cache-size

		 * https://forums.raspberrypi.com/viewtopic.php?t=98428

		 */



		v7_cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0xf00>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		v7_cpu1: cpu@1 {
@@ -53,6 +68,13 @@ v7_cpu1: cpu@1 { 
			compatible = "arm,cortex-a7";

			reg = <0xf01>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		v7_cpu2: cpu@2 {
@@ -60,6 +82,13 @@ v7_cpu2: cpu@2 { 
			compatible = "arm,cortex-a7";

			reg = <0xf02>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		v7_cpu3: cpu@3 {
@@ -67,6 +96,27 @@ v7_cpu3: cpu@3 { 
			compatible = "arm,cortex-a7";

			reg = <0xf03>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		/* Source for cache-line-size + cache-sets

		 * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System

		 * /About-the-L2-Memory-system?lang=en

		 * Source for cache-size

		 * https://forums.raspberrypi.com/viewtopic.php?t=98428

		 */

		l2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set

			cache-level = <2>;

		};

	};

};