Commit 4f47c91f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-ingenic' into clk-next 

 - Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock
   Jitter Cleaner With Dual Loop PLLs
 - Support secure mode of STM32MP1 SoCs
 - Improve clock support for Actions S500 SoC

* clk-lmk04832:
  clk: lmk04832: Use of match table
  clk: lmk04832: Depend on SPI
  clk: lmk04832: add support for digital delay
  clk: add support for the lmk04832
  dt-bindings: clock: add ti,lmk04832 bindings

* clk-stm:
  clk: stm32mp1: new compatible for secure RCC support
  dt-bindings: clock: stm32mp1 new compatible for secure rcc
  dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15
  dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
  dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
  reset: stm32mp1: remove stm32mp1 reset
  clk: stm32mp1: move RCC reset controller into RCC clock driver
  clk: stm32mp1: convert to module driver
  clk: stm32mp1: remove intermediate pll clocks
  clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
  clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock

* clk-rohm:
  clk: bd718xx: Drop BD70528 support

* clk-actions:
  clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC
  dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
  clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
  clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
  clk: actions: Fix SD clocks factor table on Owl S500 SoC
  clk: actions: Fix UART clock dividers on Owl S500 SoC

* clk-ingenic:
  clk: ingenic: Add support for the JZ4760
  clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
  clk: ingenic: Remove pll_info.no_bypass_bit
  clk: ingenic: Read bypass register only when there is one
  clk: Support bypassing dividers
  dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles
parents e51fbc55 bf68fdfd 21e74330 fa5b6541 db01868f bdbfc029

Documentation/devicetree/bindings/clock/ingenic,cgu.yaml

+4 −0
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ select: 
        enum:

          - ingenic,jz4740-cgu

          - ingenic,jz4725b-cgu

          - ingenic,jz4760-cgu

          - ingenic,jz4760b-cgu

          - ingenic,jz4770-cgu

          - ingenic,jz4780-cgu

          - ingenic,x1000-cgu
@@ -49,6 +51,8 @@ properties: 
      - enum:

          - ingenic,jz4740-cgu

          - ingenic,jz4725b-cgu

          - ingenic,jz4760-cgu

          - ingenic,jz4760b-cgu

          - ingenic,jz4770-cgu

          - ingenic,jz4780-cgu

          - ingenic,x1000-cgu

Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml

+4 −2
Original line number Diff line number Diff line
@@ -54,7 +54,9 @@ properties: 


  compatible:

    items:

      - const: st,stm32mp1-rcc

      - enum:

          - st,stm32mp1-rcc-secure

          - st,stm32mp1-rcc

      - const: syscon



  reg:
@@ -71,7 +73,7 @@ additionalProperties: false 
examples:

  - |

    rcc: rcc@50000000 {

        compatible = "st,stm32mp1-rcc", "syscon";

        compatible = "st,stm32mp1-rcc-secure", "syscon";

        reg = <0x50000000 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

Documentation/devicetree/bindings/clock/ti,lmk04832.yaml

0 → 100644
+209 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Clock bindings for the Texas Instruments LMK04832



maintainers:

  - Liam Beguin <liambeguin@gmail.com>



description: |

  Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B

  support. The LMK04832 is pin compatible with the LMK0482x family.



  Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf



properties:

  compatible:

    enum:

      - ti,lmk04832



  reg:

    maxItems: 1



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



  '#clock-cells':

    const: 1



  spi-max-frequency:

    maximum: 5000000



  clocks:

    items:

      - description: PLL2 reference clock.



  clock-names:

    items:

      - const: oscin



  reset-gpios:

    maxItems: 1



  ti,spi-4wire-rdbk:

    description: |

      Select SPI 4wire readback pin configuration.

      Available readback pins are,

        CLKin_SEL0 0

        CLKin_SEL1 1

        RESET 2

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2]

    default: 1



  ti,vco-hz:

    description: Optional to set VCO frequency of the PLL in Hertz.



  ti,sysref-ddly:

    description: SYSREF digital delay value.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 8

    maximum: 8191

    default: 8



  ti,sysref-mux:

    description: |

      SYSREF Mux configuration.

      Available options are,

        Normal SYNC 0

        Re-clocked 1

        SYSREF Pulser 2

        SYSREF Continuous 3

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2, 3]

    default: 3



  ti,sync-mode:

    description: SYNC pin configuration.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2]

    default: 1



  ti,sysref-pulse-count:

    description:

      Number of SYSREF pulses to send when SYSREF is not in continuous mode.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [1, 2, 4, 8]

    default: 4



patternProperties:

  "@[0-9a-d]+$":

    type: object

    description:

      Child nodes used to configure output clocks.



    properties:

      reg:

        description:

          clock output identifier.

        minimum: 0

        maximum: 13



      ti,clkout-fmt:

        description:

          Clock output format.

          Available options are,

            Powerdown 0x00

            LVDS 0x01

            HSDS 6 mA 0x02

            HSDS 8 mA 0x03

            LVPECL 1600 mV 0x04

            LVPECL 2000 mV 0x05

            LCPECL 0x06

            CML 16 mA 0x07

            CML 24 mA 0x08

            CML 32 mA 0x09

            CMOS (Off/Inverted) 0x0a

            CMOS (Normal/Off) 0x0b

            CMOS (Inverted/Inverted) 0x0c

            CMOS (Inverted/Normal) 0x0d

            CMOS (Normal/Inverted) 0x0e

            CMOS (Normal/Normal) 0x0f

        $ref: /schemas/types.yaml#/definitions/uint32

        minimum: 0

        maximum: 15



      ti,clkout-sysref:

        description:

          Select SYSREF clock path for output clock.

        type: boolean



    required:

      - reg



    additionalProperties: false



required:

  - compatible

  - reg

  - '#clock-cells'

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    clocks {

        lmk04832_oscin: oscin {

            compatible = "fixed-clock";



            #clock-cells = <0>;

            clock-frequency = <122880000>;

            clock-output-names = "lmk04832-oscin";

        };

    };



    spi0 {

        #address-cells = <1>;

        #size-cells = <0>;



        lmk04832: clock-controller@0 {

            #address-cells = <1>;

            #size-cells = <0>;



            reg = <0>;



            compatible = "ti,lmk04832";

            spi-max-frequency = <781250>;



            reset-gpios = <&gpio_lmk 0 0 0>;



            #clock-cells = <1>;

            clocks = <&lmk04832_oscin>;

            clock-names = "oscin";



            ti,spi-4wire-rdbk = <0>;

            ti,vco-hz = <2457600000>;



            assigned-clocks =

                <&lmk04832 0>, <&lmk04832 1>,

                <&lmk04832 2>, <&lmk04832 3>,

                <&lmk04832 4>,

                <&lmk04832 6>, <&lmk04832 7>,

                <&lmk04832 10>, <&lmk04832 11>;

            assigned-clock-rates =

                <122880000>, <384000>,

                <122880000>, <384000>,

                <122880000>,

                <153600000>, <384000>,

                <614400000>, <384000>;



            clkout0@0 {

                reg = <0>;

                ti,clkout-fmt = <0x01>; // LVDS

            };



            clkout1@1 {

                reg = <1>;

                ti,clkout-fmt = <0x01>; // LVDS

                ti,clkout-sysref;

            };

        };

    };

drivers/clk/Kconfig

+21 −3
Original line number Diff line number Diff line
@@ -51,6 +51,14 @@ config CLK_HSDK 
	  This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs

	  control.



config LMK04832

	tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"

	depends on SPI

	select REGMAP_SPI

	help

	  Say yes here to build support for Texas Instruments' LMK04832 Ultra

	  Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs



config COMMON_CLK_MAX77686

	tristate "Clock driver for Maxim 77620/77686/77802 MFD"

	depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
@@ -331,6 +339,16 @@ config COMMON_CLK_STM32MP157 
	help

	  Support for stm32mp157 SoC family clocks



config COMMON_CLK_STM32MP157_SCMI

	bool "stm32mp157 Clock driver with Trusted Firmware"

	depends on COMMON_CLK_STM32MP157

	select COMMON_CLK_SCMI

	select ARM_SCMI_PROTOCOL

	default y

	help

	  Support for stm32mp157 SoC family clocks with Trusted Firmware using

	  SCMI protocol.



config COMMON_CLK_STM32F

	def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)

	help
@@ -354,10 +372,10 @@ config COMMON_CLK_MMP2_AUDIO 


config COMMON_CLK_BD718XX

	tristate "Clock driver for 32K clk gates on ROHM PMICs"

	depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828

	depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828

	help

	  This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and

	  ROHM BD70528 PMICs clock gates.

	  This driver supports ROHM BD71837, BD71847, BD71850, BD71815

	  and BD71828 PMICs clock gates.



config COMMON_CLK_FIXED_MMIO

	bool "Clock driver for Memory Mapped Fixed values"

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o 
obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o

obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o

obj-$(CONFIG_COMMON_CLK_K210)		+= clk-k210.o

obj-$(CONFIG_LMK04832)			+= clk-lmk04832.o

obj-$(CONFIG_COMMON_CLK_LOCHNAGAR)	+= clk-lochnagar.o

obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o

obj-$(CONFIG_COMMON_CLK_MAX9485)	+= clk-max9485.o