Commit e51fbc55 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and... 

Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk-socfpga' into clk-next

* clk-rockchip:
  clk: rockchip: export ACLK_VCODEC for RK3036
  clk: rockchip: fix rk3568 cpll clk gate bits
  clk: rockchip: Optimize PLL table memory usage

* clk-amlogic:
  clk: meson: g12a: Add missing NNA source clocks for g12b
  clk: meson: axg-audio: improve deferral handling
  clk: meson: g12a: fix gp0 and hifi ranges
  clk: meson: pll: switch to determine_rate for the PLL ops

* clk-yaml:
  dt-bindings: clock: gpio-mux-clock: Convert to json-schema

* clk-zynq:
  clk: zynqmp: Handle divider specific read only flag
  clk: zynqmp: Use firmware specific mux clock flags
  clk: zynqmp: Use firmware specific divider clock flags
  clk: zynqmp: Use firmware specific common clock flags
  clk: zynqmp: pll: Remove some dead code
  clk: zynqmp: fix compile testing without ZYNQMP_FIRMWARE

* clk-socfpga:
  clk: socfpga: clk-pll: Remove unused variable 'rc'
  clk: agilex/stratix10/n5x: fix how the bypass_reg is handled
  clk: agilex/stratix10: add support for the 2nd bypass
  clk: agilex/stratix10: fix bypass representation
  clk: agilex/stratix10: remove noc_clk
parents 029eae23 14de023d 686f2250 feb29cc7 03aea91b 99c6fc6d

Documentation/devicetree/bindings/clock/gpio-mux-clock.txt

deleted100644 → 0
+0 −19
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Binding for simple gpio clock multiplexer.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "gpio-mux-clock".

- clocks: list of two references to parent clocks.

- #clock-cells : from common clock binding; shall be set to 0.

- select-gpios : GPIO reference for selecting the parent clock.



Example:

	clock {

		compatible = "gpio-mux-clock";

		clocks = <&parentclk1>, <&parentclk2>;

		#clock-cells = <0>;

		select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;

	};

Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml

0 → 100644
+45 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Simple GPIO clock multiplexer



maintainers:

  - Sergej Sawazki <ce3a@gmx.de>



properties:

  compatible:

    const: gpio-mux-clock



  clocks:

    items:

      - description: First parent clock

      - description: Second parent clock



  '#clock-cells':

    const: 0



  select-gpios:

    description: GPIO reference for selecting the parent clock.

    maxItems: 1



required:

  - compatible

  - clocks

  - '#clock-cells'

  - select-gpios



additionalProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>



    clock {

            compatible = "gpio-mux-clock";

            clocks = <&parentclk1>, <&parentclk2>;

            #clock-cells = <0>;

            select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;

    };

drivers/clk/meson/axg-audio.c

+2 −3
Original line number Diff line number Diff line
@@ -1665,8 +1665,7 @@ static int devm_clk_get_enable(struct device *dev, char *id) 
	clk = devm_clk_get(dev, id);

	if (IS_ERR(clk)) {

		ret = PTR_ERR(clk);

		if (ret != -EPROBE_DEFER)

			dev_err(dev, "failed to get %s", id);

		dev_err_probe(dev, ret, "failed to get %s", id);

		return ret;

	}
@@ -1811,7 +1810,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) 


	ret = device_reset(dev);

	if (ret) {

		dev_err(dev, "failed to reset device\n");

		dev_err_probe(dev, ret, "failed to reset device\n");

		return ret;

	}

drivers/clk/meson/clk-pll.c

+15 −11
Original line number Diff line number Diff line
@@ -242,8 +242,8 @@ static int meson_clk_get_pll_settings(unsigned long rate, 
	return best ? 0 : -EINVAL;

}



static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,

				     unsigned long *parent_rate)

static int meson_clk_pll_determine_rate(struct clk_hw *hw,

					struct clk_rate_request *req)

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
@@ -251,22 +251,26 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
	unsigned long round;

	int ret;



	ret = meson_clk_get_pll_settings(rate, *parent_rate, &m, &n, pll);

	ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,

					 &m, &n, pll);

	if (ret)

		return meson_clk_pll_recalc_rate(hw, *parent_rate);

		return ret;



	round = __pll_params_to_rate(*parent_rate, m, n, 0, pll);

	round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);



	if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)

		return round;

	if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {

		req->rate = round;

		return 0;

	}



	/*

	 * The rate provided by the setting is not an exact match, let's

	 * try to improve the result using the fractional parameter

	 */

	frac = __pll_params_with_frac(rate, *parent_rate, m, n, pll);

	frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);

	req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);



	return __pll_params_to_rate(*parent_rate, m, n, frac, pll);

	return 0;

}



static int meson_clk_pll_wait_lock(struct clk_hw *hw)
@@ -419,7 +423,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
 */

const struct clk_ops meson_clk_pcie_pll_ops = {

	.recalc_rate	= meson_clk_pll_recalc_rate,

	.round_rate	= meson_clk_pll_round_rate,

	.determine_rate	= meson_clk_pll_determine_rate,

	.is_enabled	= meson_clk_pll_is_enabled,

	.enable		= meson_clk_pcie_pll_enable,

	.disable	= meson_clk_pll_disable
@@ -429,7 +433,7 @@ EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops); 
const struct clk_ops meson_clk_pll_ops = {

	.init		= meson_clk_pll_init,

	.recalc_rate	= meson_clk_pll_recalc_rate,

	.round_rate	= meson_clk_pll_round_rate,

	.determine_rate	= meson_clk_pll_determine_rate,

	.set_rate	= meson_clk_pll_set_rate,

	.is_enabled	= meson_clk_pll_is_enabled,

	.enable		= meson_clk_pll_enable,

drivers/clk/meson/g12a.c

+7 −1
Original line number Diff line number Diff line
@@ -1603,7 +1603,7 @@ static struct clk_regmap g12b_cpub_clk_trace = { 
};



static const struct pll_mult_range g12a_gp0_pll_mult_range = {

	.min = 55,

	.min = 125,

	.max = 255,

};
@@ -4723,6 +4723,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { 
		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,

		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,

		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,

		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,

		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,

		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,

		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,

		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,

		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,