Unverified Commit 53415957 authored by Mark Brown's avatar Mark Brown
Browse files

Add support for Intel Thunder Bay SPI controller 

Merge series from nandhini.srikandan@intel.com <nandhini.srikandan@intel.com>:

This patch enables support for DW SPI on Intel Thunder Bay.  This patch
set also enables master mode for latest Designware SPI versions.  The
driver is tested on Keem Bay and Thunder Bay evaluation board.
parents 1ed34d36 dc4e6d9f

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml

+2 −0
Original line number Diff line number Diff line
@@ -61,6 +61,8 @@ properties: 
          - const: snps,dw-apb-ssi

      - description: Intel Keem Bay SPI Controller

        const: intel,keembay-ssi

      - description: Intel Thunder Bay SPI Controller

        const: intel,thunderbay-ssi

      - description: Baikal-T1 SPI Controller

        const: baikal,bt1-ssi

      - description: Baikal-T1 System Boot SPI Controller

drivers/spi/spi-dw-core.c

+3 −2
Original line number Diff line number Diff line
@@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) 
		if (spi->mode & SPI_LOOP)

			cr0 |= DW_HSSI_CTRLR0_SRL;



		if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)

			cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;

		/* CTRLR0[31] MST */

		if (dw_spi_ver_is_ge(dws, HSSI, 102A))

			cr0 |= DW_HSSI_CTRLR0_MST;

	}



	return cr0;

drivers/spi/spi-dw-mmio.c

+4 −4
Original line number Diff line number Diff line
@@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev, 
	return 0;

}



static int dw_spi_keembay_init(struct platform_device *pdev,

static int dw_spi_intel_init(struct platform_device *pdev,

			     struct dw_spi_mmio *dwsmmio)

{

	dwsmmio->dws.ip = DW_HSSI_ID;

	dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST;



	return 0;

}
@@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { 
	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},

	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},

	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},

	{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},

	{ .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},

	{ .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},

	{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},

	{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},

	{ /* end of table */}

drivers/spi/spi-dw.h

+3 −10
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
	((_dws)->ip == DW_ ## _ip ## _ID)



#define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \

	(dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ver)

	(dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)



#define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
@@ -31,8 +31,7 @@ 


/* DW SPI controller capabilities */

#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)

#define DW_SPI_CAP_KEEMBAY_MST		BIT(1)

#define DW_SPI_CAP_DFS32		BIT(2)

#define DW_SPI_CAP_DFS32		BIT(1)



/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */

#define DW_SPI_CTRLR0			0x00
@@ -94,13 +93,7 @@ 
#define DW_HSSI_CTRLR0_SCPOL			BIT(9)

#define DW_HSSI_CTRLR0_TMOD_MASK		GENMASK(11, 10)

#define DW_HSSI_CTRLR0_SRL			BIT(13)



/*

 * For Keem Bay, CTRLR0[31] is used to select controller mode.

 * 0: SSI is slave

 * 1: SSI is master

 */

#define DW_HSSI_CTRLR0_KEEMBAY_MST		BIT(31)

#define DW_HSSI_CTRLR0_MST			BIT(31)



/* Bit fields in CTRLR1 */

#define DW_SPI_NDF_MASK				GENMASK(15, 0)