Commit 57afdc0a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-fixes' 



Yuji Ishikawa says:

====================
net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode

This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
It is composed of two parts:

* 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
* 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.

  net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL
    v1 -> v2:
      - added Fixes tag to commit message

  net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
    v1 -> v2:
      - added Fixes tag to commit message
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6cee105e 0959bc4b

drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c

+26 −16
Original line number Diff line number Diff line
@@ -22,21 +22,21 @@ 
#define ETHER_CLK_SEL_RMII_CLK_EN BIT(2)

#define ETHER_CLK_SEL_RMII_CLK_RST BIT(3)

#define ETHER_CLK_SEL_DIV_SEL_2 BIT(4)

#define ETHER_CLK_SEL_DIV_SEL_20 BIT(0)

#define ETHER_CLK_SEL_DIV_SEL_20 0

#define ETHER_CLK_SEL_FREQ_SEL_125M	(BIT(9) | BIT(8))

#define ETHER_CLK_SEL_FREQ_SEL_50M	BIT(9)

#define ETHER_CLK_SEL_FREQ_SEL_25M	BIT(8)

#define ETHER_CLK_SEL_FREQ_SEL_2P5M	0

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN BIT(0)

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN 0

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC BIT(10)

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV BIT(11)

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN  BIT(0)

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN  0

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC BIT(12)

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV BIT(13)

#define ETHER_CLK_SEL_TX_CLK_O_TX_I	 BIT(0)

#define ETHER_CLK_SEL_TX_CLK_O_TX_I	 0

#define ETHER_CLK_SEL_TX_CLK_O_RMII_I	 BIT(14)

#define ETHER_CLK_SEL_TX_O_E_N_IN	 BIT(15)

#define ETHER_CLK_SEL_RMII_CLK_SEL_IN	 BIT(0)

#define ETHER_CLK_SEL_RMII_CLK_SEL_IN	 0

#define ETHER_CLK_SEL_RMII_CLK_SEL_RX_C	 BIT(16)



#define ETHER_CLK_SEL_RX_TX_CLK_EN (ETHER_CLK_SEL_RX_CLK_EN | ETHER_CLK_SEL_TX_CLK_EN)
@@ -96,30 +96,40 @@ static void visconti_eth_fix_mac_speed(void *priv, unsigned int speed) 
	val |= ETHER_CLK_SEL_TX_O_E_N_IN;

	writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



	/* Set Clock-Mux, Start clock, Set TX_O direction */

	switch (dwmac->phy_intf_sel) {

	case ETHER_CONFIG_INTF_RGMII:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	case ETHER_CONFIG_INTF_RMII:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |

			ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RMII_CLK_RST;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	case ETHER_CONFIG_INTF_MII:

	default:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |

			ETHER_CLK_SEL_RMII_CLK_EN;

		break;

	}



	/* Start clock */

	writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

	val |= ETHER_CLK_SEL_RX_TX_CLK_EN;

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



	val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;

		val |= ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	}



	spin_unlock_irqrestore(&dwmac->lock, flags);

}