iommu/vt-d: Add 256-bit invalidation descriptor support
Intel vt-d spec rev3.0 requires software to use 256-bit descriptors in invalidation queue. As the spec reads in section 6.5.2: Remapping hardware supporting Scalable Mode Translations (ECAP_REG.SMTS=1) allow software to additionally program the width of the descriptors (128-bits or 256-bits) that will be written into the Queue. Software should setup the Invalidation Queue for 256-bit descriptors before progra- mming remapping hardware for scalable-mode translation as 128-bit descriptors are treated as invalid descriptors (see Table 21 in Section 6.5.2.10) in scalable-mode. This patch adds 256-bit invalidation descriptor support if the hardware presents scalable mode capability. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Signed-off-by:Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by:
Liu Yi L <yi.l.liu@intel.com> Signed-off-by:
Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by:
Joerg Roedel <jroedel@suse.de>
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- drivers/iommu/dmar.c 61 additions, 30 deletionsdrivers/iommu/dmar.c
- drivers/iommu/intel-svm.c 49 additions, 27 deletionsdrivers/iommu/intel-svm.c
- drivers/iommu/intel_irq_remapping.c 4 additions, 2 deletionsdrivers/iommu/intel_irq_remapping.c
- include/linux/intel-iommu.h 7 additions, 2 deletionsinclude/linux/intel-iommu.h
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