Commit 60ece833 authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Vinod Koul
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phy: ralink: phy-mt7621-pci: use kernel clock APIS 



MT7621 SoC clock driver has already mainlined in
'commit 48df7a26 ("clk: ralink: add clock driver for mt7621 SoC")'
This allow us to properly use kernel clock apis to get
the clock frequency needed for the phy configuration
instead of use custom architecture code to do the same.

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-4-sergio.paracuellos@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 77945a34

drivers/phy/ralink/phy-mt7621-pci.c

+20 −13
Original line number Original line Diff line number Diff line
@@ -5,6 +5,7 @@ 
 */

 */





#include <dt-bindings/phy/phy.h>

#include <dt-bindings/phy/phy.h>

#include <linux/clk.h>

#include <linux/bitfield.h>

#include <linux/bitfield.h>

#include <linux/bitops.h>

#include <linux/bitops.h>

#include <linux/module.h>

#include <linux/module.h>
@@ -14,8 +15,6 @@ 
#include <linux/platform_device.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/regmap.h>

#include <linux/sys_soc.h>

#include <linux/sys_soc.h>

#include <mt7621.h>

#include <ralink_regs.h>





#define RG_PE1_PIPE_REG				0x02c

#define RG_PE1_PIPE_REG				0x02c

#define RG_PE1_PIPE_RST				BIT(12)

#define RG_PE1_PIPE_RST				BIT(12)
@@ -62,8 +61,6 @@ 




#define RG_PE1_FRC_MSTCKDIV			BIT(5)

#define RG_PE1_FRC_MSTCKDIV			BIT(5)





#define XTAL_MASK				GENMASK(8, 6)



#define MAX_PHYS	2

#define MAX_PHYS	2





/**

/**
@@ -71,6 +68,7 @@ 
 * @dev: pointer to device

 * @dev: pointer to device

 * @regmap: kernel regmap pointer

 * @regmap: kernel regmap pointer

 * @phy: pointer to the kernel PHY device

 * @phy: pointer to the kernel PHY device

 * @sys_clk: pointer to the system XTAL clock

 * @port_base: base register

 * @port_base: base register

 * @has_dual_port: if the phy has dual ports.

 * @has_dual_port: if the phy has dual ports.

 * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'

 * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
@@ -80,6 +78,7 @@ struct mt7621_pci_phy { 
	struct device *dev;

	struct device *dev;

	struct regmap *regmap;

	struct regmap *regmap;

	struct phy *phy;

	struct phy *phy;

	struct clk *sys_clk;

	void __iomem *port_base;

	void __iomem *port_base;

	bool has_dual_port;

	bool has_dual_port;

	bool bypass_pipe_rst;

	bool bypass_pipe_rst;
@@ -116,12 +115,14 @@ static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) 
	}

	}

}

}





static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)

static int mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)

{

{

	struct device *dev = phy->dev;

	struct device *dev = phy->dev;

	u32 xtal_mode;

	unsigned long clk_rate;





	xtal_mode = FIELD_GET(XTAL_MASK, rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0));

	clk_rate = clk_get_rate(phy->sys_clk);

	if (!clk_rate)

		return -EINVAL;





	/* Set PCIe Port PHY to disable SSC */

	/* Set PCIe Port PHY to disable SSC */

	/* Debug Xtal Type */

	/* Debug Xtal Type */
@@ -139,13 +140,13 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) 
			       RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);

			       RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);

	}

	}





	if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */

	if (clk_rate == 40000000) { /* 40MHz Xtal */

		/* Set Pre-divider ratio (for host mode) */

		/* Set Pre-divider ratio (for host mode) */

		mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV,

		mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV,

			       FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01));

			       FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01));





		dev_dbg(dev, "Xtal is 40MHz\n");

		dev_dbg(dev, "Xtal is 40MHz\n");

	} else if (xtal_mode >= 6) { /* 25MHz Xal */

	} else if (clk_rate == 25000000) { /* 25MHz Xal */

		mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV,

		mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV,

			       FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00));

			       FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00));
@@ -196,13 +197,15 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) 
	mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR,

	mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR,

		       FIELD_PREP(RG_PE1_H_PLL_BR, 0x00));

		       FIELD_PREP(RG_PE1_H_PLL_BR, 0x00));





	if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */

	if (clk_rate == 40000000) { /* 40MHz Xtal */

		/* set force mode enable of da_pe1_mstckdiv */

		/* set force mode enable of da_pe1_mstckdiv */

		mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,

		mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,

			       RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,

			       RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,

			       FIELD_PREP(RG_PE1_MSTCKDIV, 0x01) |

			       FIELD_PREP(RG_PE1_MSTCKDIV, 0x01) |

			       RG_PE1_FRC_MSTCKDIV);

			       RG_PE1_FRC_MSTCKDIV);

	}

	}



	return 0;

}

}





static int mt7621_pci_phy_init(struct phy *phy)

static int mt7621_pci_phy_init(struct phy *phy)
@@ -212,9 +215,7 @@ static int mt7621_pci_phy_init(struct phy *phy) 
	if (mphy->bypass_pipe_rst)

	if (mphy->bypass_pipe_rst)

		mt7621_bypass_pipe_rst(mphy);

		mt7621_bypass_pipe_rst(mphy);





	mt7621_set_phy_for_ssc(mphy);

	return mt7621_set_phy_for_ssc(mphy);



	return 0;

}

}





static int mt7621_pci_phy_power_on(struct phy *phy)

static int mt7621_pci_phy_power_on(struct phy *phy)
@@ -324,6 +325,12 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev) 
		return PTR_ERR(phy->phy);

		return PTR_ERR(phy->phy);

	}

	}





	phy->sys_clk = devm_clk_get(dev, NULL);

	if (IS_ERR(phy->sys_clk)) {

		dev_err(dev, "failed to get phy clock\n");

		return PTR_ERR(phy->sys_clk);

	}



	phy_set_drvdata(phy->phy, phy);

	phy_set_drvdata(phy->phy, phy);





	provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);

	provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);