Commit 65b462fc authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: enable GENERIC0_INT for gfx/compute pipes 



To generate an interrupt to RLC for accessing indirect
registers that CP can not access directly

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b21348a2

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+8 −0
Original line number Diff line number Diff line
@@ -5689,12 +5689,16 @@ gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 
		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

					    TIME_STAMP_INT_ENABLE, 0);

		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

					    GENERIC0_INT_ENABLE, 0);

		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

		break;

	case AMDGPU_IRQ_STATE_ENABLE:

		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

					    TIME_STAMP_INT_ENABLE, 1);

		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

					    GENERIC0_INT_ENABLE, 1);

		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

		break;

	default:
@@ -5742,12 +5746,16 @@ static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev 
		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

					     TIME_STAMP_INT_ENABLE, 0);

		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

					     GENERIC0_INT_ENABLE, 0);

		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

		break;

	case AMDGPU_IRQ_STATE_ENABLE:

		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

					     TIME_STAMP_INT_ENABLE, 1);

		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

					     GENERIC0_INT_ENABLE, 1);

		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

		break;

	default: