Commit 678d536b authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: dac: ad5449: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 8341dc04 ("iio:dac: Add support for the ad5449")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-47-jic23@kernel.org
parent d2b240d3

drivers/iio/dac/ad5449.c

+2 −2
Original line number Diff line number Diff line
@@ -68,10 +68,10 @@ struct ad5449 { 
	uint16_t dac_cache[AD5449_MAX_CHANNELS];



	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 */

	__be16 data[2] ____cacheline_aligned;

	__be16 data[2] __aligned(IIO_DMA_MINALIGN);

};



enum ad5449_type {