Commit d2b240d3 authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: dac: ad5421: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 5691b234 ("staging:iio:dac: Add AD5421 driver")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-46-jic23@kernel.org
parent 94ec314e

drivers/iio/dac/ad5421.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -72,13 +72,13 @@ struct ad5421_state { 
	struct mutex			lock;

	struct mutex			lock;





	/*

	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 * transfer buffers to live in their own cache lines.

	 */

	 */

	union {

	union {

		__be32 d32;

		__be32 d32;

		u8 d8[4];

		u8 d8[4];

	} data[2] ____cacheline_aligned;

	} data[2] __aligned(IIO_DMA_MINALIGN);

};

};





static const struct iio_event_spec ad5421_current_event[] = {

static const struct iio_event_spec ad5421_current_event[] = {