Commit 73e2b72a authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees 



Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 83b7f0b8

arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -968,6 +968,7 @@ pmc@7000e400 { 
		nvidia,core-pwr-off-time = <0>;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;

		core-supply = <&vdd_core>;

	};



	ahub@70080000 {

arch/arm/boot/dts/tegra30-beaver.dts

+1 −0
Original line number Diff line number Diff line
@@ -1916,6 +1916,7 @@ pmc@7000e400 { 
		nvidia,core-pwr-off-time = <0>;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;

		core-supply = <&core_vdd_reg>;

	};



	ahub@70080000 {

arch/arm/boot/dts/tegra30-cardhu.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -393,6 +393,7 @@ pmc@7000e400 { 
		nvidia,core-pwr-off-time = <0>;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;

		core-supply = <&vdd_core>;

	};



	ahub@70080000 {

arch/arm/boot/dts/tegra30-colibri.dtsi

+14 −3
Original line number Diff line number Diff line
@@ -767,9 +767,14 @@ vdd1_reg: vdd1 { 


				vddctrl_reg: vddctrl {

					regulator-name = "+V1.0_VDD_CPU";

					regulator-min-microvolt = <1150000>;

					regulator-max-microvolt = <1150000>;

					regulator-min-microvolt = <800000>;

					regulator-max-microvolt = <1250000>;

					regulator-coupled-with = <&vdd_core>;

					regulator-coupled-max-spread = <300000>;

					regulator-max-step-microvolt = <100000>;

					regulator-always-on;



					nvidia,tegra-cpu-regulator;

				};



				reg_1v8_vio: vio {
@@ -892,15 +897,20 @@ temp-sensor@4c { 
		};



		/* SW: +V1.2_VDD_CORE */

		regulator@60 {

		vdd_core: regulator@60 {

			compatible = "ti,tps62362";

			reg = <0x60>;



			regulator-name = "tps62362-vout";

			regulator-min-microvolt = <900000>;

			regulator-max-microvolt = <1400000>;

			regulator-coupled-with = <&vddctrl_reg>;

			regulator-coupled-max-spread = <300000>;

			regulator-max-step-microvolt = <100000>;

			regulator-boot-on;

			regulator-always-on;



			nvidia,tegra-core-regulator;

		};

	};
@@ -913,6 +923,7 @@ pmc@7000e400 { 
		nvidia,core-pwr-off-time = <0>;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;

		core-supply = <&vdd_core>;



		/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */

		i2c-thermtrip {

arch/arm/boot/dts/tegra30-ouya.dts

+1 −0
Original line number Diff line number Diff line
@@ -2195,6 +2195,7 @@ pmc@7000e400 { 
		nvidia,core-pwr-off-time = <458>;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;

		core-supply = <&vdd_core>;

	};



	memory-controller@7000f000 {