Commit 77a4ea53 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
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drm/amd/display: change bw_dceip and bw_vbios into pointers 



-Change bw_calcs_dceip into pointer
-Change bw_calcs_vbios into pointer

This is needed for flattening of core_dc into dc, as without this the
diags build fails

Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 391e20d8

drivers/gpu/drm/amd/display/dc/core/dc.c

+26 −0
Original line number Diff line number Diff line
@@ -433,6 +433,13 @@ static void destruct(struct core_dc *dc) 


	dm_free(dc->ctx);

	dc->ctx = NULL;



	dm_free(dc->bw_vbios);

	dc->bw_vbios = NULL;



	dm_free(dc->bw_dceip);

	dc->bw_dceip = NULL;



}



static bool construct(struct core_dc *dc,
@@ -440,8 +447,25 @@ static bool construct(struct core_dc *dc, 
{

	struct dal_logger *logger;

	struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));

	struct bw_calcs_dceip *dc_dceip = dm_alloc(sizeof(*dc_dceip));

	struct bw_calcs_vbios *dc_vbios = dm_alloc(sizeof(*dc_vbios));



	enum dce_version dc_version = DCE_VERSION_UNKNOWN;



	if (!dc_dceip) {

		dm_error("%s: failed to create dceip\n", __func__);

		goto dceip_fail;

	}



	dc->bw_dceip = dc_dceip;



	if (!dc_vbios) {

		dm_error("%s: failed to create vbios\n", __func__);

		goto vbios_fail;

	}



	dc->bw_vbios = dc_vbios;



	if (!dc_ctx) {

		dm_error("%s: failed to create ctx\n", __func__);

		goto ctx_fail;
@@ -544,6 +568,8 @@ static bool construct(struct core_dc *dc, 
logger_fail:

val_ctx_fail:

ctx_fail:

dceip_fail:

vbios_fail:

	destruct(dc);

	return false;

}

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+1 −1
Original line number Diff line number Diff line
@@ -1264,7 +1264,7 @@ void dce110_set_displaymarks( 
			continue;



		total_dest_line_time_ns = compute_pstate_blackout_duration(

			dc->bw_vbios.blackout_duration, pipe_ctx->stream);

			dc->bw_vbios->blackout_duration, pipe_ctx->stream);

		pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(

			pipe_ctx->plane_res.mi,

			context->bw.dce.nbp_state_change_wm_ns[num_pipes],

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+17 −17
Original line number Diff line number Diff line
@@ -826,8 +826,8 @@ static bool dce110_validate_bandwidth( 


	if (bw_calcs(

			dc->ctx,

			&dc->bw_dceip,

			&dc->bw_vbios,

			dc->bw_dceip,

			dc->bw_vbios,

			context->res_ctx.pipe_ctx,

			dc->res_pool->pipe_count,

			&context->bw.dce))
@@ -1127,21 +1127,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
			DM_PP_CLOCK_TYPE_ENGINE_CLK,

			&clks);

	/* convert all the clock fro kHz to fix point mHz */

	dc->bw_vbios.high_sclk = bw_frc_to_fixed(

	dc->bw_vbios->high_sclk = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels-1], 1000);

	dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels/8], 1000);

	dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels*2/8], 1000);

	dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels*3/8], 1000);

	dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels*4/8], 1000);

	dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels*5/8], 1000);

	dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels*6/8], 1000);

	dc->bw_vbios.low_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[0], 1000);

	dc->sclk_lvls = clks;
@@ -1150,11 +1150,11 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
			dc->ctx,

			DM_PP_CLOCK_TYPE_DISPLAY_CLK,

			&clks);

	dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(

	dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels-1], 1000);

	dc->bw_vbios.mid_voltage_max_dispclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels>>1], 1000);

	dc->bw_vbios.low_voltage_max_dispclk  = bw_frc_to_fixed(

	dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(

			clks.clocks_in_khz[0], 1000);



	/*do memory clock*/
@@ -1163,12 +1163,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
			DM_PP_CLOCK_TYPE_MEMORY_CLK,

			&clks);



	dc->bw_vbios.low_yclk = bw_frc_to_fixed(

	dc->bw_vbios->low_yclk = bw_frc_to_fixed(

		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);

	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(

	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,

		1000);

	dc->bw_vbios.high_yclk = bw_frc_to_fixed(

	dc->bw_vbios->high_yclk = bw_frc_to_fixed(

		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,

		1000);

}
@@ -1353,7 +1353,7 @@ static bool construct( 


	dc->public.caps.max_planes =  pool->base.pipe_count;



	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);

	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);



	bw_calcs_data_update_from_pplib(dc);

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

+25 −25
Original line number Diff line number Diff line
@@ -771,8 +771,8 @@ bool dce112_validate_bandwidth( 


	if (bw_calcs(

			dc->ctx,

			&dc->bw_dceip,

			&dc->bw_vbios,

			dc->bw_dceip,

			dc->bw_vbios,

			context->res_ctx.pipe_ctx,

			dc->res_pool->pipe_count,

			&context->bw.dce))
@@ -1018,21 +1018,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
				DM_PP_CLOCK_TYPE_ENGINE_CLK,

				&clks);

		/* convert all the clock fro kHz to fix point mHz */

		dc->bw_vbios.high_sclk = bw_frc_to_fixed(

		dc->bw_vbios->high_sclk = bw_frc_to_fixed(

				clks.clocks_in_khz[clks.num_levels-1], 1000);

		dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(

		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(

				clks.clocks_in_khz[clks.num_levels/8], 1000);

		dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(

		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(

				clks.clocks_in_khz[clks.num_levels*2/8], 1000);

		dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(

		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(

				clks.clocks_in_khz[clks.num_levels*3/8], 1000);

		dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(

		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(

				clks.clocks_in_khz[clks.num_levels*4/8], 1000);

		dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(

		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(

				clks.clocks_in_khz[clks.num_levels*5/8], 1000);

		dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(

		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(

				clks.clocks_in_khz[clks.num_levels*6/8], 1000);

		dc->bw_vbios.low_sclk  = bw_frc_to_fixed(

		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(

				clks.clocks_in_khz[0], 1000);



		/*do memory clock*/
@@ -1041,12 +1041,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
				DM_PP_CLOCK_TYPE_MEMORY_CLK,

				&clks);



		dc->bw_vbios.low_yclk = bw_frc_to_fixed(

		dc->bw_vbios->low_yclk = bw_frc_to_fixed(

			clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);

		dc->bw_vbios.mid_yclk = bw_frc_to_fixed(

		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,

			1000);

		dc->bw_vbios.high_yclk = bw_frc_to_fixed(

		dc->bw_vbios->high_yclk = bw_frc_to_fixed(

			clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,

			1000);
@@ -1054,21 +1054,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
	}



	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */

	dc->bw_vbios.high_sclk = bw_frc_to_fixed(

	dc->bw_vbios->high_sclk = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);

	dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);

	dc->bw_vbios.low_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(

			eng_clks.data[0].clocks_in_khz, 1000);



	/*do memory clock*/
@@ -1082,12 +1082,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):

	 * YCLK = UMACLK*m_memoryTypeMultiplier

	 */

	dc->bw_vbios.low_yclk = bw_frc_to_fixed(

	dc->bw_vbios->low_yclk = bw_frc_to_fixed(

		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);

	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(

	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,

		1000);

	dc->bw_vbios.high_yclk = bw_frc_to_fixed(

	dc->bw_vbios->high_yclk = bw_frc_to_fixed(

		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,

		1000);
@@ -1325,7 +1325,7 @@ static bool construct( 
	if (!dce112_hw_sequencer_construct(dc))

		goto res_create_fail;



	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);

	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);



	bw_calcs_data_update_from_pplib(dc);

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

+12 −12
Original line number Diff line number Diff line
@@ -729,21 +729,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
	}



	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */

	dc->bw_vbios.high_sclk = bw_frc_to_fixed(

	dc->bw_vbios->high_sclk = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);

	dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);

	dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(

		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);

	dc->bw_vbios.low_sclk  = bw_frc_to_fixed(

	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(

			eng_clks.data[0].clocks_in_khz, 1000);



	/*do memory clock*/
@@ -770,12 +770,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 
	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):

	 * YCLK = UMACLK*m_memoryTypeMultiplier

	 */

	dc->bw_vbios.low_yclk = bw_frc_to_fixed(

	dc->bw_vbios->low_yclk = bw_frc_to_fixed(

		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);

	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(

	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,

		1000);

	dc->bw_vbios.high_yclk = bw_frc_to_fixed(

	dc->bw_vbios->high_yclk = bw_frc_to_fixed(

		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,

		1000);
@@ -984,7 +984,7 @@ static bool construct( 


	dc->public.caps.max_planes =  pool->base.pipe_count;



	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);

	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);



	bw_calcs_data_update_from_pplib(dc);