Commit 7857825b authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: SubVP missing scaling case 



[Description]
For SubVP scaling case we have to combine
the plane scaling and stream scaling.

Use UCLK dummy p-state WM for FCLK WM set C

[Description]
For DCN32/321 program dummy UCLK P-state watermark into FCLK
watermark set C register.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b09c1fff

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+8 −2
Original line number Diff line number Diff line
@@ -634,7 +634,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, 
			&cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];

	struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;

	struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;

	uint32_t out_num, out_den;

	uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;



	pipe_data->mode = SUBVP;

	pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
@@ -651,8 +651,14 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, 
	/* Calculate the scaling factor from the src and dst height.

	 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.

	 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"

	 *

	 * Make sure to combine stream and plane scaling together.

	 */

	reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, &out_num, &out_den);

	reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,

			&out_num_stream, &out_den_stream);

	reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,

			&out_num_plane, &out_den_plane);

	reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);

	pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;

	pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+5 −1
Original line number Diff line number Diff line
@@ -1796,7 +1796,11 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	/* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state.

	 * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM

	 * value.

	 */

	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;



	if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {