Unverified Commit 7b87c164 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-dts-for-v6.5-tag2' of... 

Merge tag 'renesas-dts-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.5 (take two)

  - Add IOMMU support for PCIe devices on R-Car Gen3 and RZ/G2 SoCs,
  - Add HSCIF1 serial port support on Renesas ULCB boards equipped with
    the Shimafuji Kingfisher extension,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: ulcb-kf: Add HSCIF1 node
  arm64: dts: renesas: ulcb-kf: Remove flow control for SCIF1
  ARM: dts: iwg20d-q7-common: Fix backlight pwm specifier
  arm64: dts: renesas: Add IOMMU related properties into PCIe host nodes

Link: https://lore.kernel.org/r/cover.1686304614.git.geert+renesas@glider.be


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1b84450e c776a212

arch/arm/boot/dts/iwg20d-q7-common.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ audio_clock: audio_clock { 
	lcd_backlight: backlight {

		compatible = "pwm-backlight";



		pwms = <&pwm3 0 5000000 0>;

		pwms = <&pwm3 0 5000000>;

		brightness-levels = <0 4 8 16 32 64 128 255>;

		default-brightness-level = <7>;

		enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2359,8 +2359,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2371,6 +2371,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};
@@ -2386,8 +2388,8 @@ pciec1: pcie@ee800000 { 
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2398,6 +2400,8 @@ pciec1: pcie@ee800000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			iommu-map = <0 &ipmmu_hc 1 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2238,8 +2238,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2250,6 +2250,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};
@@ -2265,8 +2267,8 @@ pciec1: pcie@ee800000 { 
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2277,6 +2279,8 @@ pciec1: pcie@ee800000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			iommu-map = <0 &ipmmu_hc 1 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -1704,8 +1704,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1716,6 +1716,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2471,8 +2471,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2483,6 +2483,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};
@@ -2498,8 +2500,8 @@ pciec1: pcie@ee800000 { 
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2510,6 +2512,8 @@ pciec1: pcie@ee800000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			iommu-map = <0 &ipmmu_hc 1 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};