Commit 7e1723fd authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS



The way hw_onecell_data is declared:
  struct clk_hw_onecell_data {
          unsigned int num;
          struct clk_hw *hws[];
  };

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_aoclk_data struct to finally get rid on the
NR_CLKS define.

[jbrunet: Fixed whitespace checkpatch warning]
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-3-38172d17c27a@linaro.org


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 141fbc27
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+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ config COMMON_CLK_MESON_CLKC_UTILS
config COMMON_CLK_MESON_AO_CLKC
	tristate
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_CLKC_UTILS
	select RESET_CONTROLLER

config COMMON_CLK_MESON_EE_CLKC
+22 −22
Original line number Diff line number Diff line
@@ -288,8 +288,7 @@ static struct clk_regmap *axg_aoclk_regmap[] = {
	&axg_aoclk_saradc_gate,
};

static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
	.hws = {
static struct clk_hw *axg_aoclk_hw_clks[] = {
	[CLKID_AO_REMOTE]	= &axg_aoclk_remote.hw,
	[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master.hw,
	[CLKID_AO_I2C_SLAVE]	= &axg_aoclk_i2c_slave.hw,
@@ -307,8 +306,6 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
	[CLKID_AO_32K_SEL]	= &axg_aoclk_32k_sel.hw,
	[CLKID_AO_32K]		= &axg_aoclk_32k.hw,
	[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
	},
	.num = NR_CLKS,
};

static const struct meson_aoclk_data axg_aoclkc_data = {
@@ -317,7 +314,10 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
	.reset		= axg_aoclk_reset,
	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
	.clks		= axg_aoclk_regmap,
	.hw_data	= &axg_aoclk_onecell_data,
	.hw_clks	= {
		.hws	= axg_aoclk_hw_clks,
		.num	= ARRAY_SIZE(axg_aoclk_hw_clks),
	},
};

static const struct of_device_id axg_aoclkc_match_table[] = {
+0 −2
Original line number Diff line number Diff line
@@ -10,8 +10,6 @@
#ifndef __AXG_AOCLKC_H
#define __AXG_AOCLKC_H

#define NR_CLKS	17

#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/reset/axg-aoclkc.h>

+34 −34
Original line number Diff line number Diff line
@@ -411,8 +411,7 @@ static struct clk_regmap *g12a_aoclk_regmap[] = {
	&g12a_aoclk_saradc_gate,
};

static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
	.hws = {
static struct clk_hw *g12a_aoclk_hw_clks[] = {
	[CLKID_AO_AHB]		= &g12a_aoclk_ahb.hw,
	[CLKID_AO_IR_IN]	= &g12a_aoclk_ir_in.hw,
	[CLKID_AO_I2C_M0]	= &g12a_aoclk_i2c_m0.hw,
@@ -442,8 +441,6 @@ static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
	[CLKID_AO_CEC_SEL]	= &g12a_aoclk_cec_sel.hw,
	[CLKID_AO_CEC]		= &g12a_aoclk_cec.hw,
	[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
	},
	.num = NR_CLKS,
};

static const struct meson_aoclk_data g12a_aoclkc_data = {
@@ -452,7 +449,10 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
	.reset		= g12a_aoclk_reset,
	.num_clks	= ARRAY_SIZE(g12a_aoclk_regmap),
	.clks		= g12a_aoclk_regmap,
	.hw_data	= &g12a_aoclk_onecell_data,
	.hw_clks	= {
		.hws	= g12a_aoclk_hw_clks,
		.num	= ARRAY_SIZE(g12a_aoclk_hw_clks),
	},
};

static const struct of_device_id g12a_aoclkc_match_table[] = {
+0 −2
Original line number Diff line number Diff line
@@ -24,8 +24,6 @@
#define CLKID_AO_CEC_DIV	25
#define CLKID_AO_CEC_SEL	26

#define NR_CLKS	29

#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/reset/g12a-aoclkc.h>

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