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Commit 834f1d6c authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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ARM: dts: tegra20: paz00: Add memory timings



PAZ00 board has two variants of DDR2 SDRAM devices for External Memory:
one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H.
The Micron variant doesn't have official timings in the wild, hence only
timings for the Hynix are added. The memory frequency-scaling was tested
using the Tegra20 devfreq driver.

Tested-by: default avatarMarc Dietrich <marvin24@gmx.de>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent ceffd104
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