Commit 86d904b6 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Geert Uytterhoeven
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arm64: dts: renesas: Add IOMMU related properties into PCIe host nodes 



Add iommu-map and iommu-map-mask properties to the PCIe host nodes.
Note that iommu-map-mask should be zero because the IPMMU assigns
one micro TLB ID only, to the PCIe host.

Also change the dma-ranges arguments for IOMMU.  Note that dma-ranges
can be used if the IOMMU is disabled.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230510090358.261266-1-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 18cbbdd8

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2359,8 +2359,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2371,6 +2371,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};
@@ -2386,8 +2388,8 @@ pciec1: pcie@ee800000 { 
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2398,6 +2400,8 @@ pciec1: pcie@ee800000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			iommu-map = <0 &ipmmu_hc 1 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2238,8 +2238,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2250,6 +2250,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};
@@ -2265,8 +2267,8 @@ pciec1: pcie@ee800000 { 
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2277,6 +2279,8 @@ pciec1: pcie@ee800000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			iommu-map = <0 &ipmmu_hc 1 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -1704,8 +1704,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1716,6 +1716,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2471,8 +2471,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2483,6 +2483,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};
@@ -2498,8 +2500,8 @@ pciec1: pcie@ee800000 { 
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2510,6 +2512,8 @@ pciec1: pcie@ee800000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			iommu-map = <0 &ipmmu_hc 1 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};

arch/arm64/boot/dts/renesas/r8a77951.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2778,8 +2778,8 @@ pciec0: pcie@fe000000 { 
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2790,6 +2790,8 @@ pciec0: pcie@fe000000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			iommu-map = <0 &ipmmu_hc 0 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};
@@ -2805,8 +2807,8 @@ pciec1: pcie@ee800000 { 
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;

			/* Map all possible DDR/IOMMU as inbound ranges */

			dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2817,6 +2819,8 @@ pciec1: pcie@ee800000 { 
			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			iommu-map = <0 &ipmmu_hc 1 1>;

			iommu-map-mask = <0>;

			status = "disabled";

		};