Commit 933c8a93 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add gfx ip block for sienna_cichlid (v3) 



Add support for GC 10.3.

v2: Squash in gb_addr_config fix (Alex)
v3: Add num_pkrs support (Alex)

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 757b3af8

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+1 −0
Original line number Diff line number Diff line
@@ -134,6 +134,7 @@ struct gb_addr_config { 
	uint8_t num_banks;

	uint8_t num_se;

	uint8_t num_rb_per_se;

	uint8_t num_pkrs;

};



struct amdgpu_gfx_config {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+15 −0
Original line number Diff line number Diff line
@@ -63,6 +63,9 @@ 
#define mmCGTT_GS_NGG_CLK_CTRL	0x5087

#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1



#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8

#define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L



MODULE_FIRMWARE("amdgpu/navi10_ce.bin");

MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");

MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -4002,6 +4005,16 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 
		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

		break;

	case CHIP_SIENNA_CICHLID:

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

		adev->gfx.config.sc_hiz_tile_fifo_size = 0;

		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

		adev->gfx.config.gb_addr_config_fields.num_pkrs =

			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);

		break;

	default:

		BUG();

		break;
@@ -4107,6 +4120,7 @@ static int gfx_v10_0_sw_init(void *handle) 
	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_SIENNA_CICHLID:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;
@@ -8253,6 +8267,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 
	switch (adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_SIENNA_CICHLID:

		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;

		break;

	case CHIP_NAVI12:

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −0
Original line number Diff line number Diff line
@@ -487,6 +487,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		break;

	default:

		return -EINVAL;