Commit 94ec314e authored by Jonathan Cameron's avatar Jonathan Cameron
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iio: dac: ad5360: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: a3e2940c ("staging:iio:dac: Add AD5360 driver")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-45-jic23@kernel.org
parent 8779b88c

drivers/iio/dac/ad5360.c

+2 −2
Original line number Diff line number Diff line
@@ -79,13 +79,13 @@ struct ad5360_state { 
	struct mutex			lock;



	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 */

	union {

		__be32 d32;

		u8 d8[4];

	} data[2] ____cacheline_aligned;

	} data[2] __aligned(IIO_DMA_MINALIGN);

};



enum ad5360_type {