Commit a3d66a76 authored by Pali Rohár's avatar Pali Rohár Committed by Marc Zyngier
Browse files

irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x 



Register ARMADA_370_XP_INT_FABRIC_MASK_OFFS is Armada 370 and XP specific
and on new Armada platforms it has different meaning. It does not configure
Performance Counter Overflow interrupt masking. So do not touch this
register on non-A370/XP platforms (A375, A38x and A39x).

Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Cc: stable@vger.kernel.org
Fixes: 28da06df ("irqchip: armada-370-xp: Enable the PMU interrupts")
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425113706.29310-1-pali@kernel.org
parent 4c5b2be1

drivers/irqchip/irq-armada-370-xp.c

+10 −1
Original line number Diff line number Diff line
@@ -327,7 +327,16 @@ static inline int armada_370_xp_msi_init(struct device_node *node, 


static void armada_xp_mpic_perf_init(void)

{

	unsigned long cpuid = cpu_logical_map(smp_processor_id());

	unsigned long cpuid;



	/*

	 * This Performance Counter Overflow interrupt is specific for

	 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.

	 */

	if (!of_machine_is_compatible("marvell,armada-370-xp"))

		return;



	cpuid = cpu_logical_map(smp_processor_id());



	/* Enable Performance Counter Overflow interrupts */

	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),