Commit a6dd1206 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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arm64: dts: qcom: sm8450: add display hardware devices 



Add devices tree nodes describing display hardware on SM8450:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs

This does not provide support for DP controllers present on SM8450.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-3-dmitry.baryshkov@linaro.org
parent a5ac24ba

arch/arm64/boot/dts/qcom/sm8450.dtsi

+279 −4
Original line number Diff line number Diff line
@@ -2646,6 +2646,281 @@ camcc: clock-controller@ade0000 { 
			status = "disabled";

		};



		mdss: display-subsystem@ae00000 {

			compatible = "qcom,sm8450-mdss";

			reg = <0 0x0ae00000 0 0x1000>;

			reg-names = "mdss";



			/* same path used twice */

			interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,

					<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;

			interconnect-names = "mdp0-mem", "mdp1-mem";



			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;



			power-domains = <&dispcc MDSS_GDSC>;



			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

				 <&gcc GCC_DISP_HF_AXI_CLK>,

				 <&gcc GCC_DISP_SF_AXI_CLK>,

				 <&dispcc DISP_CC_MDSS_MDP_CLK>;



			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <1>;



			iommus = <&apps_smmu 0x2800 0x402>;



			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			status = "disabled";



			mdss_mdp: display-controller@ae01000 {

				compatible = "qcom,sm8450-dpu";

				reg = <0 0x0ae01000 0 0x8f000>,

				      <0 0x0aeb0000 0 0x2008>;

				reg-names = "mdp", "vbif";



				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

					<&gcc GCC_DISP_SF_AXI_CLK>,

					<&dispcc DISP_CC_MDSS_AHB_CLK>,

					<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

					<&dispcc DISP_CC_MDSS_MDP_CLK>,

					<&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				clock-names = "bus",

					      "nrt_bus",

					      "iface",

					      "lut",

					      "core",

					      "vsync";



				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				assigned-clock-rates = <19200000>;



				operating-points-v2 = <&mdp_opp_table>;

				power-domains = <&rpmhpd SM8450_MMCX>;



				interrupt-parent = <&mdss>;

				interrupts = <0>;



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						dpu_intf1_out: endpoint {

							remote-endpoint = <&mdss_dsi0_in>;

						};

					};



					port@1 {

						reg = <1>;

						dpu_intf2_out: endpoint {

							remote-endpoint = <&mdss_dsi1_in>;

						};

					};



				};



				mdp_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-172000000 {

						opp-hz = /bits/ 64 <172000000>;

						required-opps = <&rpmhpd_opp_low_svs_d1>;

					};



					opp-200000000 {

						opp-hz = /bits/ 64 <200000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-325000000 {

						opp-hz = /bits/ 64 <325000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-375000000 {

						opp-hz = /bits/ 64 <375000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-500000000 {

						opp-hz = /bits/ 64 <500000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



			mdss_dsi0: dsi@ae94000 {

				compatible = "qcom,mdss-dsi-ctrl";

				reg = <0 0x0ae94000 0 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <4>;



				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,

					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,

					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					<&gcc GCC_DISP_HF_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";



				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;

				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;



				operating-points-v2 = <&mdss_dsi_opp_table>;

				power-domains = <&rpmhpd SM8450_MMCX>;



				phys = <&mdss_dsi0_phy>;

				phy-names = "dsi";



				#address-cells = <1>;

				#size-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						mdss_dsi0_in: endpoint {

							remote-endpoint = <&dpu_intf1_out>;

						};

					};



					port@1 {

						reg = <1>;

						mdss_dsi0_out: endpoint {

						};

					};

				};



				mdss_dsi_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-187500000 {

						opp-hz = /bits/ 64 <187500000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-300000000 {

						opp-hz = /bits/ 64 <300000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-358000000 {

						opp-hz = /bits/ 64 <358000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};

				};

			};



			mdss_dsi0_phy: phy@ae94400 {

				compatible = "qcom,dsi-phy-5nm-8450";

				reg = <0 0x0ae94400 0 0x200>,

				      <0 0x0ae94600 0 0x280>,

				      <0 0x0ae94900 0 0x260>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				#clock-cells = <1>;

				#phy-cells = <0>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&rpmhcc RPMH_CXO_CLK>;

				clock-names = "iface", "ref";



				status = "disabled";

			};



			mdss_dsi1: dsi@ae96000 {

				compatible = "qcom,mdss-dsi-ctrl";

				reg = <0 0x0ae96000 0 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <5>;



				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,

					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,

					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&gcc GCC_DISP_HF_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";



				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;

				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;



				operating-points-v2 = <&mdss_dsi_opp_table>;

				power-domains = <&rpmhpd SM8450_MMCX>;



				phys = <&mdss_dsi1_phy>;

				phy-names = "dsi";



				#address-cells = <1>;

				#size-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						mdss_dsi1_in: endpoint {

							remote-endpoint = <&dpu_intf2_out>;

						};

					};



					port@1 {

						reg = <1>;

						mdss_dsi1_out: endpoint {

						};

					};

				};

			};



			mdss_dsi1_phy: phy@ae96400 {

				compatible = "qcom,dsi-phy-5nm-8450";

				reg = <0 0x0ae96400 0 0x200>,

				      <0 0x0ae96600 0 0x280>,

				      <0 0x0ae96900 0 0x260>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				#clock-cells = <1>;

				#phy-cells = <0>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&rpmhcc RPMH_CXO_CLK>;

				clock-names = "iface", "ref";



				status = "disabled";

			};

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,sm8450-dispcc";

			reg = <0 0x0af00000 0 0x20000>;
@@ -2653,10 +2928,10 @@ dispcc: clock-controller@af00000 { 
				 <&rpmhcc RPMH_CXO_CLK_A>,

				 <&gcc GCC_DISP_AHB_CLK>,

				 <&sleep_clk>,

				 <0>, /* dsi0 */

				 <0>,

				 <0>, /* dsi1 */

				 <0>,

				 <&mdss_dsi0_phy 0>,

				 <&mdss_dsi0_phy 1>,

				 <&mdss_dsi1_phy 0>,

				 <&mdss_dsi1_phy 1>,

				 <0>, /* dp0 */

				 <0>,

				 <0>, /* dp1 */