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Commit a789ed5f authored by Jeremy Fitzhardinge's avatar Jeremy Fitzhardinge
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xen: cache cr0 value to avoid trap'n'emulate for read_cr0



stts() is implemented in terms of read_cr0/write_cr0 to update the
state of the TS bit.  This happens during context switch, and so
is fairly performance critical.  Rather than falling back to
a trap-and-emulate native read_cr0, implement our own by caching
the last-written value from write_cr0 (the TS bit is the only one
we really care about).

Impact: optimise Xen context switches
Signed-off-by: default avatarJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
parent b80119bb
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