Commit b6f18aa8 authored by Aswath Govindraju's avatar Aswath Govindraju Committed by Vignesh Raghavendra
Browse files

arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node 



Add PCIe1 RC device tree node for the single PCIe instance present on
the J721S2.

Reviewed-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: default avatarAswath Govindraju <a-govindraju@ti.com>
Signed-off-by: default avatarMatt Ranostay <mranostay@ti.com>
Signed-off-by: default avatarRavi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: default avatarRoger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-8-r-gunasekaran@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent bbabba4e

arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

+43 −0
Original line number Diff line number Diff line
@@ -847,6 +847,49 @@ serdes0: serdes@5060000 { 
		};

	};



	pcie1_rc: pcie@2910000 {

		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";

		reg = <0x00 0x02910000 0x00 0x1000>,

		      <0x00 0x02917000 0x00 0x400>,

		      <0x00 0x0d800000 0x00 0x800000>,

		      <0x00 0x18000000 0x00 0x1000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;

		device_type = "pci";

		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;

		max-link-speed = <3>;

		num-lanes = <4>;

		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 276 41>;

		clock-names = "fck";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xff>;

		vendor-id = <0x104c>;

		device-id = <0xb013>;

		msi-map = <0x0 &gic_its 0x0 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,

			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */

				<0 0 0 2 &pcie1_intc 0>, /* INT B */

				<0 0 0 3 &pcie1_intc 0>, /* INT C */

				<0 0 0 4 &pcie1_intc 0>; /* INT D */



		status = "disabled"; /* Needs gpio and serdes info */



		pcie1_intc: interrupt-controller {

			interrupt-controller;

			#interrupt-cells = <1>;

			interrupt-parent = <&gic500>;

			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;

		};

	};



	main_mcan0: can@2701000 {

		compatible = "bosch,m_can";

		reg = <0x00 0x02701000 0x00 0x200>,