Commit b817c931 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v5.12' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:

 - sprd: fix a macro value

 - omap: support for K3 AM64x

 - tegra: fix lockdep warnings

 - qcom: support for SDX55 and SC8180X

 - arm: fixes for sparse, kfree and void return

* tag 'mailbox-v5.12' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: arm_mhuv2: Skip calling kfree() with invalid pointer
  mailbox: tegra-hsp: Set lockdep class dynamically
  mailbox: sprd: correct definition of SPRD_OUTBOX_FIFO_FULL
  mailbox: arm_mhuv2: make remove callback return void
  mailbox: arm_mhuv2: Fix sparse warnings
  mailbox: qcom: Add support for SDX55 APCS IPC
  dt-bindings: mailbox: Add binding for SDX55 APCS
  mailbox: omap: Add support for K3 AM64x SoCs
  dt-bindings: mailbox: omap: Update binding for AM64x SoCs
  mailbox: qcom: Add SC8180X apcs compatible
  dt-bindings: mailbox: qcom: Add SC8180X APCS compatible
parents 825d1508 6b50df2b

Documentation/devicetree/bindings/mailbox/omap-mailbox.txt

+4 −0
Original line number Diff line number Diff line
@@ -28,6 +28,9 @@ SoCs has each of these instances form a cluster and combine multiple clusters 
into a single IP block present within the Main NavSS. The interrupt lines from

all these clusters are multiplexed and routed to different processor subsystems

over a limited number of common interrupt output lines of an Interrupt Router.

The AM64x SoCS also uses a single IP block comprising of multiple clusters,

but the number of clusters are smaller, and the interrupt output lines are

connected directly to various processors.



Mailbox Device Node:

====================
@@ -42,6 +45,7 @@ Required properties: 
			    "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,

						   AM43xx and DRA7xx SoCs

			    "ti,am654-mailbox" for K3 AM65x and J721E SoCs

			    "ti,am64-mailbox" for K3 AM64x SoCs

- reg:			Contains the mailbox register address range (base

			address and length)

- interrupts:		Contains the interrupt information for the mailbox

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

+34 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ properties: 
      - qcom,msm8998-apcs-hmss-global

      - qcom,qcs404-apcs-apps-global

      - qcom,sc7180-apss-shared

      - qcom,sc8180x-apss-shared

      - qcom,sdm660-apcs-hmss-global

      - qcom,sdm845-apss-shared

      - qcom,sm8150-apss-shared
@@ -33,9 +34,11 @@ properties: 


  clocks:

    description: phandles to the parent clocks of the clock driver

    minItems: 2

    items:

      - description: primary pll parent of the clock driver

      - description: auxiliary parent

      - description: reference clock



  '#mbox-cells':

    const: 1
@@ -44,9 +47,11 @@ properties: 
    const: 0



  clock-names:

    minItems: 2

    items:

      - const: pll

      - const: aux

      - const: ref



required:

  - compatible
@@ -55,6 +60,35 @@ required: 


additionalProperties: false



allOf:

  - if:

      properties:

        compatible:

          enum:

            - qcom,ipq6018-apcs-apps-global

            - qcom,ipq8074-apcs-apps-global

            - qcom,msm8916-apcs-kpss-global

            - qcom,msm8994-apcs-kpss-global

            - qcom,msm8996-apcs-hmss-global

            - qcom,msm8998-apcs-hmss-global

            - qcom,qcs404-apcs-apps-global

            - qcom,sc7180-apss-shared

            - qcom,sdm660-apcs-hmss-global

            - qcom,sdm845-apss-shared

            - qcom,sm8150-apss-shared

    then:

      properties:

        clocks:

          maxItems: 2

  - if:

      properties:

        compatible:

          enum:

            - qcom,sdx55-apcs-gcc

    then:

      properties:

        clocks:

          maxItems: 3

examples:



  # Example apcs with msm8996

drivers/mailbox/arm_mhuv2.c

+14 −12
Original line number Diff line number Diff line
@@ -238,19 +238,19 @@ struct mhuv2_mbox_chan_priv { 
};



/* Macro for reading a bitfield within a physically mapped packed struct */

#define readl_relaxed_bitfield(_regptr, _field)				\

#define readl_relaxed_bitfield(_regptr, _type, _field)			\

	({								\

		u32 _regval;						\

		_regval = readl_relaxed((_regptr));			\

		(*(typeof((_regptr)))(&_regval))._field;		\

		(*(_type *)(&_regval))._field;				\

	})



/* Macro for writing a bitfield within a physically mapped packed struct */

#define writel_relaxed_bitfield(_value, _regptr, _field)		\

#define writel_relaxed_bitfield(_value, _regptr, _type, _field)		\

	({								\

		u32 _regval;						\

		_regval = readl_relaxed(_regptr);			\

		(*(typeof(_regptr))(&_regval))._field = _value;		\

		(*(_type *)(&_regval))._field = _value;			\

		writel_relaxed(_regval, _regptr);			\

	})
@@ -496,7 +496,7 @@ static const struct mhuv2_protocol_ops mhuv2_data_transfer_ops = { 


/* Interrupt handlers */



static struct mbox_chan *get_irq_chan_comb(struct mhuv2 *mhu, u32 *reg)

static struct mbox_chan *get_irq_chan_comb(struct mhuv2 *mhu, u32 __iomem *reg)

{

	struct mbox_chan *chans = mhu->mbox.chans;

	int channel = 0, i, offset = 0, windows, protocol, ch_wn;
@@ -699,7 +699,9 @@ static irqreturn_t mhuv2_receiver_interrupt(int irq, void *arg) 
		ret = IRQ_HANDLED;

	}



	if (!IS_ERR(data))

		kfree(data);



	return ret;

}
@@ -969,8 +971,8 @@ static int mhuv2_tx_init(struct amba_device *adev, struct mhuv2 *mhu, 
	mhu->mbox.ops = &mhuv2_sender_ops;

	mhu->send = reg;



	mhu->windows = readl_relaxed_bitfield(&mhu->send->mhu_cfg, num_ch);

	mhu->minor = readl_relaxed_bitfield(&mhu->send->aidr, arch_minor_rev);

	mhu->windows = readl_relaxed_bitfield(&mhu->send->mhu_cfg, struct mhu_cfg_t, num_ch);

	mhu->minor = readl_relaxed_bitfield(&mhu->send->aidr, struct aidr_t, arch_minor_rev);



	spin_lock_init(&mhu->doorbell_pending_lock);
@@ -990,7 +992,7 @@ static int mhuv2_tx_init(struct amba_device *adev, struct mhuv2 *mhu, 
			mhu->mbox.txdone_poll = false;

			mhu->irq = adev->irq[0];



			writel_relaxed_bitfield(1, &mhu->send->int_en, chcomb);

			writel_relaxed_bitfield(1, &mhu->send->int_en, struct int_en_t, chcomb);



			/* Disable all channel interrupts */

			for (i = 0; i < mhu->windows; i++)
@@ -1023,8 +1025,8 @@ static int mhuv2_rx_init(struct amba_device *adev, struct mhuv2 *mhu, 
	mhu->mbox.ops = &mhuv2_receiver_ops;

	mhu->recv = reg;



	mhu->windows = readl_relaxed_bitfield(&mhu->recv->mhu_cfg, num_ch);

	mhu->minor = readl_relaxed_bitfield(&mhu->recv->aidr, arch_minor_rev);

	mhu->windows = readl_relaxed_bitfield(&mhu->recv->mhu_cfg, struct mhu_cfg_t, num_ch);

	mhu->minor = readl_relaxed_bitfield(&mhu->recv->aidr, struct aidr_t, arch_minor_rev);



	mhu->irq = adev->irq[0];

	if (!mhu->irq) {
@@ -1045,7 +1047,7 @@ static int mhuv2_rx_init(struct amba_device *adev, struct mhuv2 *mhu, 
		writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);



	if (mhu->minor)

		writel_relaxed_bitfield(1, &mhu->recv->int_en, chcomb);

		writel_relaxed_bitfield(1, &mhu->recv->int_en, struct int_en_t, chcomb);



	return 0;

}

drivers/mailbox/omap-mailbox.c

+5 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * OMAP mailbox driver

 *

 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.

 * Copyright (C) 2013-2019 Texas Instruments Incorporated - https://www.ti.com

 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com

 *

 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>

 *          Suman Anna <s-anna@ti.com>
@@ -663,6 +663,10 @@ static const struct of_device_id omap_mailbox_of_match[] = { 
		.compatible	= "ti,am654-mailbox",

		.data		= &omap4_data,

	},

	{

		.compatible	= "ti,am64-mailbox",

		.data		= &omap4_data,

	},

	{

		/* end */

	},

drivers/mailbox/qcom-apcs-ipc-mailbox.c

+7 −1
Original line number Diff line number Diff line
@@ -61,11 +61,15 @@ static const struct qcom_apcs_ipc_data apps_shared_apcs_data = { 
	.offset = 12, .clk_name = NULL

};



static const struct qcom_apcs_ipc_data sdx55_apcs_data = {

	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"

};



static const struct regmap_config apcs_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0xFFC,

	.max_register = 0x1008,

	.fast_io = true,

};
@@ -159,9 +163,11 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { 
	{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8998_apcs_data },

	{ .compatible = "qcom,qcs404-apcs-apps-global", .data = &msm8916_apcs_data },

	{ .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },

	{ .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },

	{ .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data },

	{ .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },

	{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },

	{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },

	{}

};

MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);