Commit bcc344a3 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update Intel nehalemep 

Update to v3, the are no TMA metrics for nehalemep.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py



to download and generate the latest events and metrics. Manually copy
the nehalemep files into perf and update mapfile.csv.

Tested on a non-nehalemep with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-20-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 1ab4ef06

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −3
Original line number Diff line number Diff line
@@ -17,9 +17,7 @@ GenuineIntel-6-3E,v21,ivytown,core 
GenuineIntel-6-2D,v21,jaketown,core

GenuineIntel-6-(57|85),v9,knightslanding,core

GenuineIntel-6-AA,v1.00,meteorlake,core

GenuineIntel-6-1E,v2,nehalemep,core

GenuineIntel-6-1F,v2,nehalemep,core

GenuineIntel-6-1A,v2,nehalemep,core

GenuineIntel-6-1[AEF],v3,nehalemep,core

GenuineIntel-6-2E,v2,nehalemex,core

GenuineIntel-6-[4589]E,v24,skylake,core

GenuineIntel-6-A[56],v24,skylake,core

tools/perf/pmu-events/arch/x86/nehalemep/cache.json

+7 −7
Original line number Diff line number Diff line
@@ -1773,7 +1773,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
@@ -1784,7 +1784,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
@@ -1795,7 +1795,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
@@ -1806,7 +1806,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
@@ -1861,7 +1861,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
@@ -1872,7 +1872,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",

tools/perf/pmu-events/arch/x86/nehalemep/memory.json

+3 −3
Original line number Diff line number Diff line
@@ -286,7 +286,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
@@ -297,7 +297,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",

        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",

        "Counter": "2",

        "EventCode": "0xB7",

        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",

tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json

+1 −1

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tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json

+1 −1

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tools/perf/pmu-events/arch/x86/nehalemep/frontend.json

+1 −1

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