Commit bf99b9b0 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: drop nv_set_ip_blocks() 



No longer used since IP enumeration is now driven by
amdgpu IP discovery code.

Acked-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7092432e

drivers/gpu/drm/amd/amdgpu/nv.c

+0 −293
Original line number Diff line number Diff line
@@ -607,304 +607,11 @@ const struct amdgpu_ip_block_version nv_common_ip_block = 
	.funcs = &nv_common_ip_funcs,

};



static int nv_reg_base_init(struct amdgpu_device *adev)

{

	int r;



	if (amdgpu_discovery) {

		r = amdgpu_discovery_reg_base_init(adev);

		if (r) {

			DRM_WARN("failed to init reg base from ip discovery table, "

					"fallback to legacy init method\n");

			goto legacy_init;

		}



		amdgpu_discovery_harvest_ip(adev);



		return 0;

	}



legacy_init:

	switch (adev->asic_type) {

	case CHIP_NAVI10:

		navi10_reg_base_init(adev);

		break;

	case CHIP_NAVI14:

		navi14_reg_base_init(adev);

		break;

	case CHIP_NAVI12:

		navi12_reg_base_init(adev);

		break;

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		sienna_cichlid_reg_base_init(adev);

		break;

	case CHIP_VANGOGH:

		vangogh_reg_base_init(adev);

		break;

	case CHIP_DIMGREY_CAVEFISH:

		dimgrey_cavefish_reg_base_init(adev);

		break;

	case CHIP_BEIGE_GOBY:

		beige_goby_reg_base_init(adev);

		break;

	case CHIP_YELLOW_CARP:

		yellow_carp_reg_base_init(adev);

		break;

	case CHIP_CYAN_SKILLFISH:

		cyan_skillfish_reg_base_init(adev);

		break;

	default:

		return -EINVAL;

	}



	return 0;

}



void nv_set_virt_ops(struct amdgpu_device *adev)

{

	adev->virt.ops = &xgpu_nv_virt_ops;

}



int nv_set_ip_blocks(struct amdgpu_device *adev)

{

	int r;



	if (adev->asic_type == CHIP_CYAN_SKILLFISH) {

		adev->nbio.funcs = &nbio_v2_3_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;

	} else if (adev->flags & AMD_IS_APU) {

		adev->nbio.funcs = &nbio_v7_2_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;

	} else {

		adev->nbio.funcs = &nbio_v2_3_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;

	}

	adev->hdp.funcs = &hdp_v5_0_funcs;



	if (adev->asic_type >= CHIP_SIENNA_CICHLID)

		adev->smuio.funcs = &smuio_v11_0_6_funcs;

	else

		adev->smuio.funcs = &smuio_v11_0_funcs;



	if (adev->asic_type == CHIP_SIENNA_CICHLID)

		adev->gmc.xgmi.supported = true;



	/* Set IP register base before any HW register access */

	r = nv_reg_base_init(adev);

	if (r)

		return r;



	switch (adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI14:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);

		if (adev->enable_mes)

			amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);

		break;

	case CHIP_NAVI12:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		if (!amdgpu_sriov_vf(adev)) {

			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		} else {

			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		}

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		if (!amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);

		break;

	case CHIP_SIENNA_CICHLID:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		if (!amdgpu_sriov_vf(adev)) {

			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		} else {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		}

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    is_support_sw_smu(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

		if (!amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);

		if (adev->enable_mes)

			amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);

		break;

	case CHIP_NAVY_FLOUNDER:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    is_support_sw_smu(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    is_support_sw_smu(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		break;

	case CHIP_VANGOGH:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);

		break;

	case CHIP_DIMGREY_CAVEFISH:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    is_support_sw_smu(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

                else if (amdgpu_device_has_dc_support(adev))

                        amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);

		break;

	case CHIP_BEIGE_GOBY:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    is_support_sw_smu(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    is_support_sw_smu(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

		break;

	case CHIP_YELLOW_CARP:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

			amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);

		amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);

		break;

	case CHIP_CYAN_SKILLFISH:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		}

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);

		break;

	default:

		return -EINVAL;

	}



	return 0;

}



static uint32_t nv_get_rev_id(struct amdgpu_device *adev)

{

	return adev->nbio.funcs->get_rev_id(adev);

drivers/gpu/drm/amd/amdgpu/nv.h

+0 −1
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ extern const struct amdgpu_ip_block_version nv_common_ip_block; 
void nv_grbm_select(struct amdgpu_device *adev,

		    u32 me, u32 pipe, u32 queue, u32 vmid);

void nv_set_virt_ops(struct amdgpu_device *adev);

int nv_set_ip_blocks(struct amdgpu_device *adev);

int navi10_reg_base_init(struct amdgpu_device *adev);

int navi14_reg_base_init(struct amdgpu_device *adev);

int navi12_reg_base_init(struct amdgpu_device *adev);