Commit c3f2801b authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS 



The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
	unsigned int num;
	struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: default avatarDmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-4-38172d17c27a@linaro.org


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 7e1723fd

drivers/clk/meson/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ config COMMON_CLK_A1_PLL 
	tristate "Amlogic A1 SoC PLL controller support"

	depends on ARM64

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_PLL

	help

	  Support for the PLL clock controller on Amlogic A113L based
@@ -119,6 +120,7 @@ config COMMON_CLK_A1_PERIPHERALS 
	depends on ARM64

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_CLKC_UTILS

	help

	  Support for the Peripherals clock controller on Amlogic A113L based

	  device, A1 SoC Family. Say Y if you want A1 Peripherals clock

drivers/clk/meson/a1-peripherals.c

+162 −161
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "a1-peripherals.h"

#include "clk-dualdiv.h"

#include "clk-regmap.h"

#include "meson-clkc-utils.h"



static struct clk_regmap xtal_in = {

	.data = &(struct clk_regmap_gate_data){
@@ -1866,8 +1867,7 @@ static MESON_GATE(rom, AXI_CLK_EN, 11); 
static MESON_GATE(prod_i2c,	AXI_CLK_EN,	12);



/* Array of all clocks registered by this provider */

static struct clk_hw_onecell_data a1_periphs_clks = {

	.hws = {

static struct clk_hw *a1_periphs_hw_clks[] = {

	[CLKID_XTAL_IN]			= &xtal_in.hw,

	[CLKID_FIXPLL_IN]		= &fixpll_in.hw,

	[CLKID_USB_PHY_IN]		= &usb_phy_in.hw,
@@ -2022,9 +2022,6 @@ static struct clk_hw_onecell_data a1_periphs_clks = { 
	[CLKID_DMC_SEL]			= &dmc_sel.hw,

	[CLKID_DMC_DIV]			= &dmc_div.hw,

	[CLKID_DMC_SEL2]		= &dmc_sel2.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

};



/* Convenience table to populate regmap in .probe */
@@ -2190,6 +2187,11 @@ static struct regmap_config a1_periphs_regmap_cfg = { 
	.reg_stride = 4,

};



static struct meson_clk_hw_data a1_periphs_clks = {

	.hws = a1_periphs_hw_clks,

	.num = ARRAY_SIZE(a1_periphs_hw_clks),

};



static int meson_a1_periphs_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;
@@ -2219,8 +2221,7 @@ static int meson_a1_periphs_probe(struct platform_device *pdev) 
					     clkid);

	}



	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,

					   &a1_periphs_clks);

	return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks);

}



static const struct of_device_id a1_periphs_clkc_match_table[] = {

drivers/clk/meson/a1-peripherals.h

+0 −1
Original line number Diff line number Diff line
@@ -108,6 +108,5 @@ 
#define CLKID_DMC_SEL		151

#define CLKID_DMC_DIV		152

#define CLKID_DMC_SEL2		153

#define NR_CLKS			154



#endif /* __A1_PERIPHERALS_H */

drivers/clk/meson/a1-pll.c

+19 −17
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/platform_device.h>

#include "a1-pll.h"

#include "clk-regmap.h"

#include "meson-clkc-utils.h"



static struct clk_regmap fixed_pll_dco = {

	.data = &(struct meson_clk_pll_data){
@@ -268,8 +269,7 @@ static struct clk_regmap fclk_div7 = { 
};



/* Array of all clocks registered by this provider */

static struct clk_hw_onecell_data a1_pll_clks = {

	.hws = {

static struct clk_hw *a1_pll_hw_clks[] = {

	[CLKID_FIXED_PLL_DCO]	= &fixed_pll_dco.hw,

	[CLKID_FIXED_PLL]	= &fixed_pll.hw,

	[CLKID_FCLK_DIV2_DIV]	= &fclk_div2_div.hw,
@@ -281,9 +281,6 @@ static struct clk_hw_onecell_data a1_pll_clks = { 
	[CLKID_FCLK_DIV5]	= &fclk_div5.hw,

	[CLKID_FCLK_DIV7]	= &fclk_div7.hw,

	[CLKID_HIFI_PLL]	= &hifi_pll.hw,

		[NR_PLL_CLKS]		= NULL,

	},

	.num = NR_PLL_CLKS,

};



static struct clk_regmap *const a1_pll_regmaps[] = {
@@ -302,6 +299,11 @@ static struct regmap_config a1_pll_regmap_cfg = { 
	.reg_stride = 4,

};



static struct meson_clk_hw_data a1_pll_clks = {

	.hws = a1_pll_hw_clks,

	.num = ARRAY_SIZE(a1_pll_hw_clks),

};



static int meson_a1_pll_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;
@@ -332,7 +334,7 @@ static int meson_a1_pll_probe(struct platform_device *pdev) 
					     clkid);

	}



	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,

	return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,

					   &a1_pll_clks);

}

drivers/clk/meson/a1-pll.h

+0 −1
Original line number Diff line number Diff line
@@ -42,6 +42,5 @@ 
#define CLKID_FCLK_DIV3_DIV	3

#define CLKID_FCLK_DIV5_DIV	4

#define CLKID_FCLK_DIV7_DIV	5

#define NR_PLL_CLKS		11



#endif /* __A1_PLL_H */