OMAP: UART: Keep the TX fifo full when possible

Current logic results in interrupt storm since the fifo
is constantly below the threshold level. Change the logic
to fill all the available spaces in the fifo as long as
we have data to minimize the possibilty of underflow and
elimiate excessive interrupts.

Signed-off-by: Dmitry Fink <finik@ti.com>
Signed-off-by: Alexander Savchenko <oleksandr.savchenko@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>