Commit c67f84e9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-next-2022-05-05' of git://anongit.freedesktop.org/drm/drm-misc into drm-next 



drm-misc-next for 5.19:

UAPI Changes:

Cross-subsystem Changes:

Core Changes:
  - Add DRM-managed mutex initialisation
  - edid: Doc improvements
  - fbdev: deferred io improvements
  - format-helper: consolidate format conversion helpers
  - gem: Rework fence handling in drm_gem_plane_helper_prepare_fb

Driver Changes:
  - ast: DisplayPort support, locking improvements
  - exynos: Revert conversion to devm_drm_of_get_bridge for DSI
  - mgag200: locking improvements
  - mxsfb: LCDIF CRC support
  - nouveau: switch to drm_gem_plane_helper_prepare_fb
  - rockchip: Refactor IOMMU initialisation, make some structures
              static, replace drm_detect_hdmi_monitor with
              drm_display_info.is_hdmi, support swapped YUV formats,
              clock improvements, rk3568 support, VOP2 support
  - bridge:
    - adv7511: Enable CEC for ADV7535
    - it6505: Send DPCD SET_POWER to monitor at disable
    - mcde_dsi: Revert conversion to devm_drm_of_get_bridge
    - tc358767: Fix for eDP and DP DT endpoint parsing
    - new bridge: i.MX8MP LDB
  - panel:
    - new panel: Startek KD070WVFPA043-C069A

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505131127.lcqvsywo7qt3eywk@houat
parents af3847a7 6071c4c2

Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8MP DPI to LVDS bridge chip



maintainers:

  - Marek Vasut <marex@denx.de>



description: |

  The i.MX8MP mediamix contains two registers which are responsible

  for configuring the on-SoC DPI-to-LVDS serializer. This describes

  those registers as bridge within the DT.



properties:

  compatible:

    const: fsl,imx8mp-ldb



  clocks:

    maxItems: 1



  clock-names:

    const: ldb



  ports:

    $ref: /schemas/graph.yaml#/properties/ports



    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Video port for DPI input.



      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description: Video port for LVDS Channel-A output (panel or bridge).



      port@2:

        $ref: /schemas/graph.yaml#/properties/port

        description: Video port for LVDS Channel-B output (panel or bridge).



    required:

      - port@0

      - port@1



required:

  - compatible

  - clocks

  - ports



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mp-clock.h>



    blk-ctrl {

        bridge {

            compatible = "fsl,imx8mp-ldb";

            clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;

            clock-names = "ldb";



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    ldb_from_lcdif2: endpoint {

                        remote-endpoint = <&lcdif2_to_ldb>;

                    };

                };



                port@1 {

                    reg = <1>;



                    ldb_lvds_ch0: endpoint {

                        remote-endpoint = <&ldb_to_lvdsx4panel>;

                    };

                };



                port@2 {

                    reg = <2>;



                    ldb_lvds_ch1: endpoint {

                    };

                };

            };

        };

    };

Documentation/devicetree/bindings/display/panel/panel-simple.yaml

+2 −0
Original line number Original line Diff line number Diff line
@@ -296,6 +296,8 @@ properties: 
      - starry,kr070pe2t

      - starry,kr070pe2t

        # Starry 12.2" (1920x1200 pixels) TFT LCD panel

        # Starry 12.2" (1920x1200 pixels) TFT LCD panel

      - starry,kr122ea0sra

      - starry,kr122ea0sra

        # Startek KD070WVFPA043-C069A 7" TFT LCD panel

      - startek,kd070wvfpa

        # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel

        # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel

      - team-source-display,tst043015cmhx

      - team-source-display,tst043015cmhx

        # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel

        # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel

Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml

+29 −17
Original line number Original line Diff line number Diff line
@@ -23,10 +23,22 @@ properties: 
      - rockchip,rk3288-dw-hdmi

      - rockchip,rk3288-dw-hdmi

      - rockchip,rk3328-dw-hdmi

      - rockchip,rk3328-dw-hdmi

      - rockchip,rk3399-dw-hdmi

      - rockchip,rk3399-dw-hdmi

      - rockchip,rk3568-dw-hdmi





  reg-io-width:

  reg-io-width:

    const: 4

    const: 4





  avdd-0v9-supply:

    description:

      A 0.9V supply that powers up the SoC internal circuitry. The actual pin name

      varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes

      HDMI_AVDD_1V0.



  avdd-1v8-supply:

    description:

      A 1.8V supply that powers up the SoC internal circuitry. The pin name on the

      SoC usually is HDMI_TX_AVDD_1V8.



  clocks:

  clocks:

    minItems: 2

    minItems: 2

    items:

    items:
@@ -36,7 +48,8 @@ properties: 
      # order when present.

      # order when present.

      - description: The HDMI CEC controller main clock

      - description: The HDMI CEC controller main clock

      - description: Power for GRF IO

      - description: Power for GRF IO

      - description: External clock for some HDMI PHY

      - description: External clock for some HDMI PHY (old clock name, deprecated)

      - description: External clock for some HDMI PHY (new name)





  clock-names:

  clock-names:

    minItems: 2

    minItems: 2
@@ -47,10 +60,14 @@ properties: 
          - cec

          - cec

          - grf

          - grf

          - vpll

          - vpll

          - ref

      - enum:

      - enum:

          - grf

          - grf

          - vpll

          - vpll

      - const: vpll

          - ref

      - enum:

          - vpll

          - ref





  ddc-i2c-bus:

  ddc-i2c-bus:

    $ref: /schemas/types.yaml#/definitions/phandle

    $ref: /schemas/types.yaml#/definitions/phandle
@@ -72,6 +89,7 @@ properties: 
      The unwedge pinctrl entry shall drive the DDC SDA line low. This is

      The unwedge pinctrl entry shall drive the DDC SDA line low. This is

      intended to work around a hardware errata that can cause the DDC I2C

      intended to work around a hardware errata that can cause the DDC I2C

      bus to be wedged.

      bus to be wedged.

    minItems: 1

    items:

    items:

      - const: default

      - const: default

      - const: unwedge

      - const: unwedge
@@ -79,27 +97,21 @@ properties: 
  ports:

  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    $ref: /schemas/graph.yaml#/properties/ports





    properties:

    patternProperties:

      port:

      "^port(@0)?$":

        $ref: /schemas/graph.yaml#/$defs/port-base

        $ref: /schemas/graph.yaml#/properties/port

        unevaluatedProperties: false

        description: Input of the DWC HDMI TX

        description: Input of the DWC HDMI TX



        properties:

        properties:

          endpoint:

            description: Connection to the VOP

          endpoint@0:

          endpoint@0:

            $ref: /schemas/graph.yaml#/properties/endpoint

            description: Connection to the VOPB

            description: Connection to the VOPB



          endpoint@1:

          endpoint@1:

            $ref: /schemas/graph.yaml#/properties/endpoint

            description: Connection to the VOPL

            description: Connection to the VOPL



    properties:

        required:

      port@1:

          - endpoint@0

        $ref: /schemas/graph.yaml#/properties/port

          - endpoint@1

        description: Output of the DWC HDMI TX



    required:

      - port





  rockchip,grf:

  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    $ref: /schemas/types.yaml#/definitions/phandle

Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml

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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip SoC display controller (VOP2)



description:

  VOP2 (Video Output Processor v2) is the display controller for the Rockchip

  series of SoCs which transfers the image data from a video memory

  buffer to an external LCD interface.



maintainers:

  - Sandy Huang <hjc@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



properties:

  compatible:

    enum:

      - rockchip,rk3566-vop

      - rockchip,rk3568-vop



  reg:

    minItems: 1

    items:

      - description:

          Must contain one entry corresponding to the base address and length

          of the register space.

      - description:

          Can optionally contain a second entry corresponding to

          the CRTC gamma LUT address.



  interrupts:

    maxItems: 1

    description:

      The VOP interrupt is shared by several interrupt sources, such as

      frame start (VSYNC), line flag and other status interrupts.



  clocks:

    items:

      - description: Clock for ddr buffer transfer.

      - description: Clock for the ahb bus to R/W the phy regs.

      - description: Pixel clock for video port 0.

      - description: Pixel clock for video port 1.

      - description: Pixel clock for video port 2.



  clock-names:

    items:

      - const: aclk

      - const: hclk

      - const: dclk_vp0

      - const: dclk_vp1

      - const: dclk_vp2



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to GRF regs used for misc control



  ports:

    $ref: /schemas/graph.yaml#/properties/ports



    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description:

          Output endpoint of VP0



      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description:

          Output endpoint of VP1



      port@2:

        $ref: /schemas/graph.yaml#/properties/port

        description:

          Output endpoint of VP2



  iommus:

    maxItems: 1



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - ports



additionalProperties: false



examples:

  - |

        #include <dt-bindings/clock/rk3568-cru.h>

        #include <dt-bindings/interrupt-controller/arm-gic.h>

        #include <dt-bindings/power/rk3568-power.h>

        bus {

            #address-cells = <2>;

            #size-cells = <2>;

            vop: vop@fe040000 {

                compatible = "rockchip,rk3568-vop";

                reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;

                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

                clocks = <&cru ACLK_VOP>,

                         <&cru HCLK_VOP>,

                         <&cru DCLK_VOP0>,

                         <&cru DCLK_VOP1>,

                         <&cru DCLK_VOP2>;

                clock-names = "aclk",

                              "hclk",

                              "dclk_vp0",

                              "dclk_vp1",

                              "dclk_vp2";

                power-domains = <&power RK3568_PD_VO>;

                iommus = <&vop_mmu>;

                vop_out: ports {

                    #address-cells = <1>;

                    #size-cells = <0>;

                    vp0: port@0 {

                        reg = <0>;

                        #address-cells = <1>;

                        #size-cells = <0>;

                    };

                    vp1: port@1 {

                        reg = <1>;

                        #address-cells = <1>;

                        #size-cells = <0>;

                    };

                    vp2: port@2 {

                        reg = <2>;

                        #address-cells = <1>;

                        #size-cells = <0>;

                    };

                };

            };

        };

Documentation/gpu/todo.rst

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@@ -603,6 +603,20 @@ Level: Advanced 
Better Testing

Better Testing

==============

==============





Add unit tests using the Kernel Unit Testing (KUnit) framework

--------------------------------------------------------------



The `KUnit <https://www.kernel.org/doc/html/latest/dev-tools/kunit/index.html>`_

provides a common framework for unit tests within the Linux kernel. Having a

test suite would allow to identify regressions earlier.



A good candidate for the first unit tests are the format-conversion helpers in

``drm_format_helper.c``.



Contact: Javier Martinez Canillas <javierm@redhat.com>



Level: Intermediate



Enable trinity for DRM

Enable trinity for DRM

----------------------

----------------------