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Commit cadf2120 authored by Paul Handrigan's avatar Paul Handrigan Committed by Mark Brown
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ASoC: cs42l73: If Internal MCLK is >= 6.4MHz, then set SCLK to 64*Fs. 



Signed-off-by: default avatarPaul Handrigan <Paul.Handrigan@cirrus.com>
Acked-by: default avatarBrian Austin <brian.austin@cirrus.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 6dbe51c2
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