Commit d2b21013 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-st', 'clk-si' and 'clk-hisilicon' into clk-next 

 - Stop using clock-output-names in ST clk drivers

* clk-st:
  dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
  clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
  dt-bindings: clock: st: clkgen-pll: add new introduced compatible
  clk: st: clkgen-pll: embed soc clock outputs within compatible data
  dt-bindings: clock: st: flexgen: add new introduced compatible
  clk: st: flexgen: embed soc clock outputs within compatible data
  clk: st: clkgen-pll: remove unused variable of struct clkgen_pll

* clk-si:
  clk: si5341: Add sysfs properties to allow checking/resetting device faults
  clk: si5341: Add silabs,iovdd-33 property
  clk: si5341: Add silabs,xaxb-ext-clk property
  clk: si5341: Allow different output VDD_SEL values
  clk: si5341: Update initialization magic
  clk: si5341: Check for input clock presence and PLL lock on startup
  clk: si5341: Avoid divide errors due to bogus register contents
  clk: si5341: Wait for DEVICE_READY on startup
  dt-bindings: clock: clk-si5341: Add new attributes

* clk-hisilicon:
  clk: hisilicon: Add clock driver for hi3559A SoC
  dt-bindings: Document the hi3559a clock bindings
parents 4f47c91f 301035c3 9b13ff43 6c819661

Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml

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+59 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Hisilicon SOC Clock for HI3559AV100



maintainers:

  - Dongjiu Geng <gengdongjiu@huawei.com>



description: |

  Hisilicon SOC clock control module which supports the clocks, resets and

  power domains on HI3559AV100.



  See also:

    dt-bindings/clock/hi3559av100-clock.h



properties:

  compatible:

    enum:

      - hisilicon,hi3559av100-clock

      - hisilicon,hi3559av100-shub-clock



  reg:

    minItems: 1

    maxItems: 2



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 2

    description: |

      First cell is reset request register offset.

      Second cell is bit offset in reset request register.



required:

  - compatible

  - reg

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@12010000 {

            compatible = "hisilicon,hi3559av100-clock";

            #clock-cells = <1>;

            #reset-cells = <2>;

            reg = <0x0 0x12010000 0x0 0x10000>;

        };

    };

...

Documentation/devicetree/bindings/clock/silabs,si5341.txt

+10 −6
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@@ -24,9 +24,8 @@ it. 


The device type, speed grade and revision are determined runtime by probing.



The driver currently only supports XTAL input mode, and does not support any

fancy input configurations. They can still be programmed into the chip and

the driver will leave them "as is".

The driver currently does not support any fancy input configurations. They can

still be programmed into the chip and the driver will leave them "as is".



==I2C device node==
@@ -45,9 +44,9 @@ Required properties: 
	corresponding to inputs. Use a fixed clock for the "xtal" input.

	At least one must be present.

- clock-names: One of: "xtal", "in0", "in1", "in2"

- vdd-supply: Regulator node for VDD



Optional properties:

- vdd-supply: Regulator node for VDD

- vdda-supply: Regulator node for VDDA

- vdds-supply: Regulator node for VDDS

- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
@@ -60,7 +59,14 @@ Optional properties: 
  be initialized, and always performs the soft-reset routine. Since this will

  temporarily stop all output clocks, don't do this if the chip is generating

  the CPU clock for example.

- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used

  in EXTCLK (external reference clock) rather than XTAL (crystal) mode.

- interrupts: Interrupt for INTRb pin.

- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V

  rather than 1.8V thresholds.

- vddoX-supply (where X is an output index): Regulator node for VDDO for the

  specified output. The driver selects the output VDD_SEL setting based on this

  voltage.

- #address-cells: shall be set to 1.

- #size-cells: shall be set to 0.
@@ -77,8 +83,6 @@ Required child node properties: 
- reg: number of clock output.



Optional child node properties:

- vdd-supply: Regulator node for VDD for this output. The driver selects default

	values for common-mode and amplitude based on the voltage.

- silabs,format: Output format, one of:

	1 = differential (defaults to LVDS levels)

	2 = low-power (defaults to HCSL levels)

Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

+3 −0
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@@ -10,7 +10,10 @@ Required properties: 


- compatible : shall be:

	"st,clkgen-pll0"

	"st,clkgen-pll0-a0"

	"st,clkgen-pll0-c0"

	"st,clkgen-pll1"

	"st,clkgen-pll1-c0"

	"st,stih407-clkgen-plla9"

	"st,stih418-clkgen-plla9"

Documentation/devicetree/bindings/clock/st/st,flexgen.txt

+10 −0
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@@ -64,6 +64,16 @@ Required properties: 
  audio use case)

  "st,flexgen-video", "st,flexgen" (enable clock propagation on parent

					and activate synchronous mode)

  "st,flexgen-stih407-a0"

  "st,flexgen-stih410-a0"

  "st,flexgen-stih407-c0"

  "st,flexgen-stih410-c0"

  "st,flexgen-stih418-c0"

  "st,flexgen-stih407-d0"

  "st,flexgen-stih410-d0"

  "st,flexgen-stih407-d2"

  "st,flexgen-stih418-d2"

  "st,flexgen-stih407-d3"



- #clock-cells : from common clock binding; shall be set to 1 (multiple clock

  outputs).

Documentation/devicetree/bindings/clock/st/st,quadfs.txt

+3 −0
Original line number Diff line number Diff line
@@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. 
Required properties:

- compatible : shall be:

  "st,quadfs"

  "st,quadfs-d0"

  "st,quadfs-d2"

  "st,quadfs-d3"

  "st,quadfs-pll"