Commit db5aa149 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.17-2022-01-26' of... 

Merge tag 'amd-drm-fixes-5.17-2022-01-26' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.17-2022-01-26:

amdgpu:
- Proper fix for otg synchronization logic regression
- DCN3.01 fixes
- Filter out secondary radeon PCI IDs
- udelay fixes
- Fix a memory leak in an error path

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220127041006.5695-1-alexander.deucher@amd.com
parents b1d83f4c 2a807341

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+81 −0
Original line number Diff line number Diff line
@@ -1525,6 +1525,87 @@ static const u16 amdgpu_unsupported_pciidlist[] = { 
	0x99A0,

	0x99A2,

	0x99A4,

	/* radeon secondary ids */

	0x3171,

	0x3e70,

	0x4164,

	0x4165,

	0x4166,

	0x4168,

	0x4170,

	0x4171,

	0x4172,

	0x4173,

	0x496e,

	0x4a69,

	0x4a6a,

	0x4a6b,

	0x4a70,

	0x4a74,

	0x4b69,

	0x4b6b,

	0x4b6c,

	0x4c6e,

	0x4e64,

	0x4e65,

	0x4e66,

	0x4e67,

	0x4e68,

	0x4e69,

	0x4e6a,

	0x4e71,

	0x4f73,

	0x5569,

	0x556b,

	0x556d,

	0x556f,

	0x5571,

	0x5854,

	0x5874,

	0x5940,

	0x5941,

	0x5b72,

	0x5b73,

	0x5b74,

	0x5b75,

	0x5d44,

	0x5d45,

	0x5d6d,

	0x5d6f,

	0x5d72,

	0x5d77,

	0x5e6b,

	0x5e6d,

	0x7120,

	0x7124,

	0x7129,

	0x712e,

	0x712f,

	0x7162,

	0x7163,

	0x7166,

	0x7167,

	0x7172,

	0x7173,

	0x71a0,

	0x71a1,

	0x71a3,

	0x71a7,

	0x71bb,

	0x71e0,

	0x71e1,

	0x71e2,

	0x71e6,

	0x71e7,

	0x71f2,

	0x7269,

	0x726b,

	0x726e,

	0x72a0,

	0x72a8,

	0x72b1,

	0x72b3,

	0x793f,

};



static const struct pci_device_id pciidlist[] = {

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

+2 −2
Original line number Diff line number Diff line
@@ -2033,10 +2033,10 @@ static void calculate_bandwidth( 
	kfree(surface_type);

free_tiling_mode:

	kfree(tiling_mode);

free_yclk:

	kfree(yclk);

free_sclk:

	kfree(sclk);

free_yclk:

	kfree(yclk);

}



/*******************************************************************************

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+0 −1
Original line number Diff line number Diff line
@@ -503,7 +503,6 @@ static void dcn_bw_calc_rq_dlg_ttu( 
	//input[in_idx].dout.output_standard;



	/*todo: soc->sr_enter_plus_exit_time??*/

	dlg_sys_param->t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;



	dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src);

	dml1_extract_rq_regs(dml, rq_regs, rq_param);

drivers/gpu/drm/amd/display/dc/core/dc.c

+27 −13
Original line number Diff line number Diff line
@@ -1404,7 +1404,20 @@ static void program_timing_sync( 
				status->timing_sync_info.master = false;



		}

		/* remove any other unblanked pipes as they have already been synced */



		/* remove any other pipes that are already been synced */

		if (dc->config.use_pipe_ctx_sync_logic) {

			/* check pipe's syncd to decide which pipe to be removed */

			for (j = 1; j < group_size; j++) {

				if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {

					group_size--;

					pipe_set[j] = pipe_set[group_size];

					j--;

				} else

					/* link slave pipe's syncd with master pipe */

					pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;

			}

		} else {

			for (j = j + 1; j < group_size; j++) {

				bool is_blanked;
@@ -1420,6 +1433,7 @@ static void program_timing_sync( 
					j--;

				}

			}

		}



		if (group_size > 1) {

			if (sync_type == TIMING_SYNCHRONIZABLE) {

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+3 −3
Original line number Diff line number Diff line
@@ -202,7 +202,7 @@ void dp_wait_for_training_aux_rd_interval( 
	uint32_t wait_in_micro_secs)

{

#if defined(CONFIG_DRM_AMD_DC_DCN)

	if (wait_in_micro_secs > 16000)

	if (wait_in_micro_secs > 1000)

		msleep(wait_in_micro_secs/1000);

	else

		udelay(wait_in_micro_secs);
@@ -6935,7 +6935,7 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table( 
			}

		}

		retries++;

		udelay(5000);

		msleep(5);

	}



	if (!result && retries == max_retries) {
@@ -6987,7 +6987,7 @@ bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link) 
			break;

		}



		udelay(5000);

		msleep(5);

	}



	if (result == ACT_FAILED) {