Commit e104df97 authored by Kajol Jain's avatar Kajol Jain Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Drop some of the JSON/events for power10 platform



Drop some of the JSON/events for power10 platform due to counter
data mismatch.

Fixes: 32daa5d7 ("perf vendor events: Initial JSON/events list for power10 platform")
Signed-off-by: default avatarKajol Jain <kjain@linux.ibm.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.ibm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20230814112803.1508296-2-kjain@linux.ibm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 3286f88f
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+0 −7
Original line number Diff line number Diff line
[
  {
    "EventCode": "0x4016E",
    "EventName": "PM_THRESH_NOT_MET",
    "BriefDescription": "Threshold counter did not meet threshold."
  }
]
+0 −10
Original line number Diff line number Diff line
@@ -19,11 +19,6 @@
    "EventName": "PM_MRK_BR_TAKEN_CMPL",
    "BriefDescription": "Marked Branch Taken instruction completed."
  },
  {
    "EventCode": "0x20112",
    "EventName": "PM_MRK_NTF_FIN",
    "BriefDescription": "The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch."
  },
  {
    "EventCode": "0x2C01C",
    "EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP",
@@ -64,11 +59,6 @@
    "EventName": "PM_L1_ICACHE_MISS",
    "BriefDescription": "Demand instruction cache miss."
  },
  {
    "EventCode": "0x30130",
    "EventName": "PM_MRK_INST_FIN",
    "BriefDescription": "marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU."
  },
  {
    "EventCode": "0x34146",
    "EventName": "PM_MRK_LD_CMPL",
+0 −5
Original line number Diff line number Diff line
@@ -29,11 +29,6 @@
    "EventName": "PM_DISP_SS0_2_INSTR_CYC",
    "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."
  },
  {
    "EventCode": "0x1F15C",
    "EventName": "PM_MRK_STCX_L2_CYC",
    "BriefDescription": "Cycles spent in the nest portion of a marked Stcx instruction. It starts counting when the operation starts to drain to the L2 and it stops counting when the instruction retires from the Instruction Completion Table (ICT) in the Instruction Sequencing Unit (ISU)."
  },
  {
    "EventCode": "0x10066",
    "EventName": "PM_ADJUNCT_CYC",
+0 −10
Original line number Diff line number Diff line
@@ -194,11 +194,6 @@
    "EventName": "PM_TLBIE_FIN",
    "BriefDescription": "TLBIE instruction finished in the LSU. Two TLBIEs can finish each cycle. All will be counted."
  },
  {
    "EventCode": "0x3D058",
    "EventName": "PM_SCALAR_FSQRT_FDIV_ISSUE",
    "BriefDescription": "Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp)."
  },
  {
    "EventCode": "0x30066",
    "EventName": "PM_LSU_FIN",
@@ -269,11 +264,6 @@
    "EventName": "PM_IC_MISS_CMPL",
    "BriefDescription": "Non-speculative instruction cache miss, counted at completion."
  },
  {
    "EventCode": "0x4D050",
    "EventName": "PM_VSU_NON_FLOP_CMPL",
    "BriefDescription": "Non-floating point VSU instructions completed."
  },
  {
    "EventCode": "0x4D052",
    "EventName": "PM_2FLOP_CMPL",
+0 −5
Original line number Diff line number Diff line
@@ -4,11 +4,6 @@
    "EventName": "PM_MRK_START_PROBE_NOP_CMPL",
    "BriefDescription": "Marked Start probe nop (AND R0,R0,R0) completed."
  },
  {
    "EventCode": "0x20016",
    "EventName": "PM_ST_FIN",
    "BriefDescription": "Store finish count. Includes speculative activity."
  },
  {
    "EventCode": "0x20018",
    "EventName": "PM_ST_FWD",