Loading drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h +2 −8 Original line number Diff line number Diff line Loading @@ -2,14 +2,8 @@ #define __NVKM_CE_H__ #include <engine/falcon.h> void gt215_ce_intr(struct nvkm_falcon *, struct nvkm_fifo_chan *); int gt215_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); extern struct nvkm_oclass gk104_ce0_oclass; extern struct nvkm_oclass gk104_ce1_oclass; extern struct nvkm_oclass gk104_ce2_oclass; extern struct nvkm_oclass gm204_ce0_oclass; extern struct nvkm_oclass gm204_ce1_oclass; extern struct nvkm_oclass gm204_ce2_oclass; int gk104_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gm204_ce_new(struct nvkm_device *, int, struct nvkm_engine **); #endif drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c +1 −1 Original line number Diff line number Diff line Loading @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include "priv.h" #include "fuc/gf100.fuc3.h" #include <nvif/class.h> Loading drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c +24 −98 Original line number Diff line number Diff line Loading @@ -21,121 +21,47 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include <engine/fifo.h> #include "priv.h" #include <nvif/class.h> static void gk104_ce_intr(struct nvkm_subdev *subdev) void gk104_ce_intr(struct nvkm_engine *ce) { const u32 base = (ce->subdev.index - NVDEV_ENGINE_CE0) * 0x1000; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; const int idx = nv_subidx(subdev) - NVDEV_ENGINE_CE0; u32 stat = nvkm_rd32(device, 0x104908 + (idx * 0x1000)); u32 stat = nvkm_rd32(device, 0x104908 + base); if (stat) { nvkm_warn(subdev, "intr %08x\n", stat); nvkm_wr32(device, 0x104908 + (idx * 0x1000), stat); nvkm_wr32(device, 0x104908 + base, stat); } } static const struct nvkm_engine_func gk104_ce = { .intr = gk104_ce_intr, .sclass = { { -1, -1, KEPLER_DMA_COPY_A }, {} } }; static int gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) int gk104_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE0", "ce0", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gk104_ce; nv_subdev(ce)->unit = 0x00000040; nv_subdev(ce)->intr = gk104_ce_intr; return 0; if (index == NVDEV_ENGINE_CE0) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00000040, true, pengine); } else if (index == NVDEV_ENGINE_CE1) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00000080, true, pengine); } else if (index == NVDEV_ENGINE_CE2) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00200000, true, pengine); } static int gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE1", "ce1", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gk104_ce; nv_subdev(ce)->unit = 0x00000080; nv_subdev(ce)->intr = gk104_ce_intr; return 0; } static int gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE2", "ce2", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gk104_ce; nv_subdev(ce)->unit = 0x00200000; nv_subdev(ce)->intr = gk104_ce_intr; return 0; return -ENODEV; } struct nvkm_oclass gk104_ce0_oclass = { .handle = NV_ENGINE(CE0, 0xe0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_ce0_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gk104_ce1_oclass = { .handle = NV_ENGINE(CE1, 0xe0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_ce1_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gk104_ce2_oclass = { .handle = NV_ENGINE(CE2, 0xe0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_ce2_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c +18 −105 Original line number Diff line number Diff line Loading @@ -21,121 +21,34 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include <engine/fifo.h> #include "priv.h" #include <nvif/class.h> static void gm204_ce_intr(struct nvkm_subdev *subdev) { struct nvkm_device *device = subdev->device; const int idx = nv_subidx(subdev) - NVDEV_ENGINE_CE0; u32 stat = nvkm_rd32(device, 0x104908 + (idx * 0x1000)); if (stat) { nvkm_warn(subdev, "intr %08x\n", stat); nvkm_wr32(device, 0x104908 + (idx * 0x1000), stat); } } static const struct nvkm_engine_func gm204_ce = { .intr = gk104_ce_intr, .sclass = { { -1, -1, MAXWELL_DMA_COPY_A }, {} } }; static int gm204_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) int gm204_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE0", "ce0", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gm204_ce; nv_subdev(ce)->unit = 0x00000040; nv_subdev(ce)->intr = gm204_ce_intr; return 0; } static int gm204_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE1", "ce1", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gm204_ce; nv_subdev(ce)->unit = 0x00000080; nv_subdev(ce)->intr = gm204_ce_intr; return 0; if (index == NVDEV_ENGINE_CE0) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00000040, true, pengine); } else if (index == NVDEV_ENGINE_CE1) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00000080, true, pengine); } else if (index == NVDEV_ENGINE_CE2) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00200000, true, pengine); } static int gm204_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE2", "ce2", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gm204_ce; nv_subdev(ce)->unit = 0x00200000; nv_subdev(ce)->intr = gm204_ce_intr; return 0; return -ENODEV; } struct nvkm_oclass gm204_ce0_oclass = { .handle = NV_ENGINE(CE0, 0x24), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_ce0_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gm204_ce1_oclass = { .handle = NV_ENGINE(CE1, 0x24), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_ce1_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gm204_ce2_oclass = { .handle = NV_ENGINE(CE2, 0x24), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_ce2_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +3 −3 Original line number Diff line number Diff line Loading @@ -21,12 +21,12 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include <engine/fifo.h> #include "priv.h" #include "fuc/gt215.fuc3.h" #include <core/client.h> #include <core/enum.h> #include <engine/fifo.h> #include <nvif/class.h> Loading @@ -43,7 +43,7 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan) { struct nvkm_subdev *subdev = &ce->engine.subdev; struct nvkm_device *device = subdev->device; const u32 base = (nv_subidx(subdev) - NVDEV_ENGINE_CE0) * 0x1000; const u32 base = (subdev->index - NVDEV_ENGINE_CE0) * 0x1000; u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; u32 mthd = (addr & 0x07ff) << 2; Loading Loading
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h +2 −8 Original line number Diff line number Diff line Loading @@ -2,14 +2,8 @@ #define __NVKM_CE_H__ #include <engine/falcon.h> void gt215_ce_intr(struct nvkm_falcon *, struct nvkm_fifo_chan *); int gt215_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); extern struct nvkm_oclass gk104_ce0_oclass; extern struct nvkm_oclass gk104_ce1_oclass; extern struct nvkm_oclass gk104_ce2_oclass; extern struct nvkm_oclass gm204_ce0_oclass; extern struct nvkm_oclass gm204_ce1_oclass; extern struct nvkm_oclass gm204_ce2_oclass; int gk104_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gm204_ce_new(struct nvkm_device *, int, struct nvkm_engine **); #endif
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c +1 −1 Original line number Diff line number Diff line Loading @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include "priv.h" #include "fuc/gf100.fuc3.h" #include <nvif/class.h> Loading
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c +24 −98 Original line number Diff line number Diff line Loading @@ -21,121 +21,47 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include <engine/fifo.h> #include "priv.h" #include <nvif/class.h> static void gk104_ce_intr(struct nvkm_subdev *subdev) void gk104_ce_intr(struct nvkm_engine *ce) { const u32 base = (ce->subdev.index - NVDEV_ENGINE_CE0) * 0x1000; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; const int idx = nv_subidx(subdev) - NVDEV_ENGINE_CE0; u32 stat = nvkm_rd32(device, 0x104908 + (idx * 0x1000)); u32 stat = nvkm_rd32(device, 0x104908 + base); if (stat) { nvkm_warn(subdev, "intr %08x\n", stat); nvkm_wr32(device, 0x104908 + (idx * 0x1000), stat); nvkm_wr32(device, 0x104908 + base, stat); } } static const struct nvkm_engine_func gk104_ce = { .intr = gk104_ce_intr, .sclass = { { -1, -1, KEPLER_DMA_COPY_A }, {} } }; static int gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) int gk104_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE0", "ce0", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gk104_ce; nv_subdev(ce)->unit = 0x00000040; nv_subdev(ce)->intr = gk104_ce_intr; return 0; if (index == NVDEV_ENGINE_CE0) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00000040, true, pengine); } else if (index == NVDEV_ENGINE_CE1) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00000080, true, pengine); } else if (index == NVDEV_ENGINE_CE2) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00200000, true, pengine); } static int gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE1", "ce1", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gk104_ce; nv_subdev(ce)->unit = 0x00000080; nv_subdev(ce)->intr = gk104_ce_intr; return 0; } static int gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE2", "ce2", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gk104_ce; nv_subdev(ce)->unit = 0x00200000; nv_subdev(ce)->intr = gk104_ce_intr; return 0; return -ENODEV; } struct nvkm_oclass gk104_ce0_oclass = { .handle = NV_ENGINE(CE0, 0xe0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_ce0_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gk104_ce1_oclass = { .handle = NV_ENGINE(CE1, 0xe0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_ce1_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gk104_ce2_oclass = { .handle = NV_ENGINE(CE2, 0xe0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_ce2_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, };
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c +18 −105 Original line number Diff line number Diff line Loading @@ -21,121 +21,34 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include <engine/fifo.h> #include "priv.h" #include <nvif/class.h> static void gm204_ce_intr(struct nvkm_subdev *subdev) { struct nvkm_device *device = subdev->device; const int idx = nv_subidx(subdev) - NVDEV_ENGINE_CE0; u32 stat = nvkm_rd32(device, 0x104908 + (idx * 0x1000)); if (stat) { nvkm_warn(subdev, "intr %08x\n", stat); nvkm_wr32(device, 0x104908 + (idx * 0x1000), stat); } } static const struct nvkm_engine_func gm204_ce = { .intr = gk104_ce_intr, .sclass = { { -1, -1, MAXWELL_DMA_COPY_A }, {} } }; static int gm204_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) int gm204_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE0", "ce0", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gm204_ce; nv_subdev(ce)->unit = 0x00000040; nv_subdev(ce)->intr = gm204_ce_intr; return 0; } static int gm204_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE1", "ce1", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gm204_ce; nv_subdev(ce)->unit = 0x00000080; nv_subdev(ce)->intr = gm204_ce_intr; return 0; if (index == NVDEV_ENGINE_CE0) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00000040, true, pengine); } else if (index == NVDEV_ENGINE_CE1) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00000080, true, pengine); } else if (index == NVDEV_ENGINE_CE2) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00200000, true, pengine); } static int gm204_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nvkm_engine *ce; int ret; ret = nvkm_engine_create(parent, engine, oclass, true, "PCE2", "ce2", &ce); *pobject = nv_object(ce); if (ret) return ret; ce->func = &gm204_ce; nv_subdev(ce)->unit = 0x00200000; nv_subdev(ce)->intr = gm204_ce_intr; return 0; return -ENODEV; } struct nvkm_oclass gm204_ce0_oclass = { .handle = NV_ENGINE(CE0, 0x24), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_ce0_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gm204_ce1_oclass = { .handle = NV_ENGINE(CE1, 0x24), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_ce1_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, }; struct nvkm_oclass gm204_ce2_oclass = { .handle = NV_ENGINE(CE2, 0x24), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_ce2_ctor, .dtor = _nvkm_engine_dtor, .init = _nvkm_engine_init, .fini = _nvkm_engine_fini, }, };
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +3 −3 Original line number Diff line number Diff line Loading @@ -21,12 +21,12 @@ * * Authors: Ben Skeggs */ #include <engine/ce.h> #include <engine/fifo.h> #include "priv.h" #include "fuc/gt215.fuc3.h" #include <core/client.h> #include <core/enum.h> #include <engine/fifo.h> #include <nvif/class.h> Loading @@ -43,7 +43,7 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan) { struct nvkm_subdev *subdev = &ce->engine.subdev; struct nvkm_device *device = subdev->device; const u32 base = (nv_subidx(subdev) - NVDEV_ENGINE_CE0) * 0x1000; const u32 base = (subdev->index - NVDEV_ENGINE_CE0) * 0x1000; u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; u32 mthd = (addr & 0x07ff) << 2; Loading