Commit f5e25a83 authored by pengzhou's avatar pengzhou Committed by Alex Deucher
Browse files

drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* 



In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: default avatarpengzhou <PengJu.Zhou@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6ba3f59e

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+19 −18
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include "mmhub/mmhub_2_0_0_default.h"

#include "navi10_enum.h"



#include "gc/gc_10_1_0_offset.h"

#include "soc15_common.h"



#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid                      0x064d
@@ -192,11 +193,11 @@ static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi 
{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];



	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

	WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

			    hub->ctx_addr_distance * vmid,

			    lower_32_bits(page_table_base));



	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

	WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

			    hub->ctx_addr_distance * vmid,

			    upper_32_bits(page_table_base));

}
@@ -207,14 +208,14 @@ static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 


	mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);



	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

		     (u32)(adev->gmc.gart_start >> 12));

	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

		     (u32)(adev->gmc.gart_start >> 44));



	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

		     (u32)(adev->gmc.gart_end >> 12));

	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

		     (u32)(adev->gmc.gart_end >> 44));

}
@@ -224,9 +225,9 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 
	uint32_t tmp;



	/* Program the AGP BAR */

	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);

	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

	WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);

	WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

	WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);



	if (!amdgpu_sriov_vf(adev)) {

		/* Program the system aperture low logical page number. */
@@ -335,7 +336,7 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 
	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);

	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);

	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);

}



static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
@@ -397,16 +398,16 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,

				    !adev->gmc.noretry);

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,

				    i * hub->ctx_distance, tmp);

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

				    i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

				    i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

				    i * hub->ctx_addr_distance,

				    lower_32_bits(adev->vm_manager.max_pfn - 1));

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

				    i * hub->ctx_addr_distance,

				    upper_32_bits(adev->vm_manager.max_pfn - 1));

	}
@@ -418,9 +419,9 @@ static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 
	unsigned i;



	for (i = 0; i < 18; ++i) {

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

				    i * hub->eng_addr_distance, 0xffffffff);

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

				    i * hub->eng_addr_distance, 0x1f);

	}

}
@@ -449,7 +450,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 


	/* Disable all tables */

	for (i = 0; i < AMDGPU_NUM_VMID; i++)

		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,

		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,

				    i * hub->ctx_distance, 0);



	/* Setup TLB control */