Skip to content
Commit fac37253 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
Browse files

KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table



Supporting hardware updates of PTE A and D bits is optional for any
RISC-V implementation so current software strategy is to always set
these bits in both G-stage (hypervisor) and VS-stage (guest kernel).

If PTE A and D bits are not set by software (hypervisor or guest)
then RISC-V implementations not supporting hardware updates of these
bits will cause traps even for perfectly valid PTEs.

Based on above explanation, the VS-stage page table created by various
KVM selftest applications is not correct because PTE A and D bits are
not set. This patch fixes VS-stage page table programming of PTE A and
D bits for KVM selftests.

Fixes: 3e06cdf1 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Tested-by: default avatarMayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 8c3ce496
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment