- Oct 01, 2010
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Madhusudhan Chikkature authored
The omap4 es2 hsmmc has a updated soft reset logic.After the reset is issued monitor a 0->1 transition first. The reset of CMD or DATA lines is complete only after a 0->1->0 transition of SRC or SRD bits. Signed-off-by:
Madhusudhan Chikkature <madhu.cr@ti.com> Tested-by:
Anand Gadiyar <gadiyar@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Grazvydas Ignotas authored
Add platform data to make use of newly added charging driver. Signed-off-by:
Grazvydas Ignotas <notasas@gmail.com> Signed-off-by:
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Grazvydas Ignotas authored
Instead of enabling the wifi module explicitly using GPIO, add a fixed regulator and hook it to MMC host card power control. This way it will only be enabled when SDIO subsystem wants to talk to it, saving power (as done by Zoom boards). Signed-off-by:
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Sanjeev Premi authored
The existing definitions for cpu revision used upper nibble in the bits[15:08]. With OMAP3630, definitions use lower nibble. This patch unifies the definitions to start at lower nibble. Signed-off-by:
Sanjeev Premi <premi@ti.com> Signed-off-by:
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Tony Lindgren authored
Otherwise the muxname passed to the function will get truncated. Based on an earlier patch by rockefeller.lin@innocomm.com. Reported-by:
<rockefeller.lin@innocomm.com> Signed-off-by:
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- Sep 29, 2010
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Kevin Hilman authored
Disable CPUfreq since 1) is not yet supported in mainline, and 2) the current driver fails to suspend properly Signed-off-by:
Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by:
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Kevin Hilman authored
In working towards a smaller default kernel, only devices used for early boot should be built in. Toward that end, build the following as modules by default: - bluetooth - audio: ALSA, ASoC - WLAN Uncompressed kernel size comparison: Before: text data bss dec hex filename 6557576 465088 5616024 12638688 c0d9e0 vmlinux After: text data bss dec hex filename 5616572 436448 5610800 11663820 b1f9cc vmlinux Signed-off-by:
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- Sep 28, 2010
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Tim Nordell authored
Enable SMSC911x Ethernet driver for LogicPD's OMAP 3530 LV SOM and OMAP 35x Torpedo board. Signed-off-by:
Tim Nordell <tim.nordell@logicpd.com> Signed-off-by:
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Tim Nordell authored
Introduce of a generic way to setup smsc911x based Ethernet controller connected to GPMC similar to gpmc-smc91x but without timing setup. Signed-off-by:
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Tim Nordell authored
Add low-level initialization for hsmmc controller for LogicPD's OMAP 3530 LV SOM and OMAP 35x Torpedo board. Signed-off-by:
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Tim Nordell authored
Adding support for LogicPD's OMAP 3530 LV SOM and OMAP 35x Torpedo board. Signed-off-by:
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matt mooney authored
Unnecessary cast from void* in assignment. Signed-off-by:
matt mooney <mfm@muteddisk.com> Acked-by:
Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by:
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- Sep 27, 2010
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Igor Grinberg authored
add support for TI HECC. Signed-off-by:
Igor Grinberg <grinberg@compulab.co.il> Signed-off-by:
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Igor Grinberg authored
add support for NAND flash. Signed-off-by:
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Igor Grinberg authored
add support for hsusb host ports 1, 2 and on-module usb hub. Signed-off-by:
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Igor Grinberg authored
add support for v3020 rtc. Signed-off-by:
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Igor Grinberg authored
Add basic suppot, enable uart and led. Signed-off-by:
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Jon Hunter authored
When changing the L3 clock frequency, the CPU is executing from internal RAM and the SDRC clock is disabled. During this time accesses made to external DDR are stalled. If the ARM subsystem attempts to access the DDR while the SDRC clock is disabled this will stall the CPU until the access to the SDRC timeouts. A timeout on the SDRC should never occur. Once a timeout occurs all the following accesses will be aborted and the DDR is no longer accessible. Although the code being executed in the internal RAM does not directly access the DDR, it was found that the branch prediction logic in the CPU may cause the CPU to prefetch code from a DDR location while the SDRC clock is disabled. This was causing an SDRC timeout which resulted in a system hang. This patch fixes this problem by ensuring the branch prediction logic is disabled while changing the L3 clock frequency. The branch prediction logic is disabled by clearing the Z-bit in the ARM CTRL register. Disabling the branch prediction logic does not have any noticable impact on the execution time of this code section. The hardware observability signals were used to monitor the sdrc idle time with and without this patch when operating at different CPU frequencies (150MHz, 500MHz and 600MHz) and the total sdrc idle time when changing frequenct was in the range of 9-11us. This was measured on an omap3430 SDP running the omapzoom p-android-omap-2.6.29 branch. Signed-off-by:
Jon Hunter <jon-hunter@ti.com> Signed-off-by:
Paul Walmsley <paul@pwsan.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Tony Lindgren <tony@atomide.com>
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Santosh Shilimkar authored
This patch has multiple fixes together. To ensure that git bisect work across commits, all changes are clubbed together 1. Move the common control base address to control core 2. Remove the manually coeded defines and use the ones from headers. 3. Fix the the status register define in id.c for OMAP4 4. Fix all the register define in hsmmc.c 5. Use the control pad accessor API for omap4 hsmmc register accesses Signed-off-by:
Benoit Cousson <b-cousson@ti.com> Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by:
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Santosh Shilimkar authored
On OMAP4, control module is divided into 4 separate IPs - OMAP44XX_CTRL_MODULE_CORE - OMAP44XX_CTRL_MODULE_PAD_CORE - OMAP44XX_CTRL_MODULE_WKUP - OMAP44XX_CTRL_MODULE_PAD_WKUP This patch adds all the omap4 control module register data and includes them in the common control.h The register data is autogenerated from the codebase thanks to Benoit Cousson efforts Signed-off-by:
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Santosh Shilimkar authored
On OMAP4 control pad are not addressable from control core base. So the common omap_ctrl_read/write APIs breaks Hence export separate APIs to manage the omap4 pad control registers. This APIs will work only for OMAP4 Signed-off-by:
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Santosh Shilimkar authored
On omap4 control module is divided in four IP blocks. - CTRL_MODULE_CORE 0x4a002000 - CTRL_MODULE_PAD_CORE 0x4a100000 - CTRL_MODULE_WKUP 0x4a30c000 - CTRL_MODULE_PAD_WKUP 0x4a31e000 Addressing all the modules with single base address is not possible considering 16 bit offsets. The mux code manages the pad core and pad wakeup related base address inside the mux framework. For other usage only control core and control pad bases are necessary. So this patch maps only needed pad control base address which is used by device drivers and infrastructure code The main control core base is still kept same in this patch to keep git-bisect working. This will be fixed in the relevant patch in this series. Signed-off-by:
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Benoit Cousson authored
Fix a few OMAP4430 clock tree problems after the recent manual merge of the various ES2 clock patches: - usim optional clock and its parent had the same name, rename the parent usim_fclk -> usim_ck - OPTFCLKEN_CLK32K is not handled anymore by the USBPHYOCP2SCP module in ES2 Create a new clock that belongs to CM_ALWON_USBPHY_CLKCTRL register This patch depends on some of the PRCM macro updates from Rajendra. Signed-off-by:
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Rajendra Nayak authored
DSS on ES2 supports only OSWR, hence remove the support for CSWR from the powerdomain framework. Signed-off-by:
Rajendra Nayak <rnayak@ti.com> Signed-off-by:
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Rajendra Nayak authored
4430 ES2 has a few new registers added and a few modified from ES1. This patch adds all the register changes in PRM and CM for OMAP4430 ES2. Signed-off-by:
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Rajendra Nayak authored
This patch updates the PRM and CM register bitshifts and masks for OMAP4430 ES2.0. Replace as well the BITFIELD macro with the shift operator in order to be consistent with the previous OMAP2 & 3 format. Sort the register list in comments in order to have a consistent register order and avoid futur change during code generation. Signed-off-by:
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Benoit Cousson authored
OMAP4 IP optional clocks require explicit enable in module CTRLCLK register. In order to allow that we have to create artificial clock nodes that represent this clock inputs in the IP. Notes: - Temporary use OMAP3 names for GPIO optional clocks until the GPIO hwmod convertion is done. It will enforce the usage of OMAP4 names as the reference. - Temporary use OMAP3 names for TIMER main clock (gptX_fck) until TIMER hwmod convertion is done. During that convertion, the new name will have to be used. Signed-off-by:
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Benoit Cousson authored
The OMAP4 hwmod data introduced the new naming convention for TI IPs (See patch OMAP4: hwmod: Add partial hwmod support for OMAP4430 ES1.0) The leaf clock names are using the same IP name and thus must be modified to match the clock populated in the hwmod data. - Fix some leaf clocks nodes that were using a _iclk instead of the _fclk prefix. - Fix some wrong interface clock name for master IPs connected to interconnect. Please not that due to the fact that nodes are sorted by name, the name change will introduce a quite ugly diff a little bit hard to follow. Timers clock con_id is still using the old gptX_fck name until the gptimer driver is updated to omap_device framework. Timers entries in hwmods DB are still disabled until the migration if timer to platform_driver + omap_hwmod. Signed-off-by:
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Rajendra Nayak authored
This patch updates the clock tree with all the changes in OMAP4430 ES2. clock nodes added -1- tie_low_clock_ck -2- abe_dpll_bypass_clk_mux_ck clock nodes deleted -1- dpll_sys_ref_clk -2- per_sgx_fclk -3- usbphyocp2scp_ick Signed-off-by:
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Lennert Buytenhek authored
update OMAP Kconfig help texts for all supported SoC models Signed-off-by:
Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by:
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Sukumar Ghorai authored
wires variable is renamed, extended and this single variable to be used to pass the platform capabilities, e.g DDR mode. Also removed the hardcoded value was using as bus-width. Signed-off-by:
Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by:
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Jarkko Nikula authored
This 'legacy' OMAP2420 McBSP2 muxing code is currently broken after recent conversion to new mux code. The omap_mcbsp_request calling this code is usually called after booting whereas the omap_mux_init_signal is __init marked so null pointer dereference would occur. Fix this by removing the muxing code and let the bootloader or board file to do it if necessary. Remove also omap2_mcbsp_ops as there is no use for it. Signed-off-by:
Jarkko Nikula <jhnikula@gmail.com> Signed-off-by:
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Peter Ujfalusi authored
McBSP SRG (Sample Rate Generator) and FSG (Frame Sync Generator) is only needed to be enabled, when McBSP is master. In McBSP slave mode, the SRG, and FSG can be kept disabled, which might save some power at the end in this configuration. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by:
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Subramaniam C.A authored
Added defines to avoid compilation error. Signed-off-by:
Subramaniam C.A <subramaniam.ca@ti.com> Acked-by:
Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by:
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Dmitry Kasatkin authored
Updates to enable omap aes Signed-off-by:
Dmitry Kasatkin <dmitry.kasatkin@nokia.com> [tony@atomide.com: updated to use CONFIG_ARCH_OMAP2/3 instead of old 24XX/34XX] Signed-off-by:
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Anand Gadiyar authored
Fix this and similar build warnings when building with omap_4430sdp_defconfig. CC arch/arm/mach-omap2/board-4430sdp.o In file included from arch/arm/mach-omap2/board-4430sdp.c:36: arch/arm/plat-omap/include/plat/usb.h:109: warning: return type defaults to 'int' Signed-off-by:
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- Sep 25, 2010
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Ricardo Salveti de Araujo authored
At Pandaboard we have 2 status leds, so adding them with similar usage as we have for Beagleboard (heartbeat and mmc0). The patch basically adds the platform data required by leds-gpio driver. Signed-off-by:
Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> Signed-off-by:
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Shubhrajyoti Datta authored
omap 4430sdp board support for the proximity sensor via GPIO keys. The proximity sensor is connected to GPIO and is registered as a GPIO key. - Making the default state of the sensor off at bootup - The init is called before platform_add_devices Signed-off-by:
Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by:
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- Sep 24, 2010
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Hema HK authored
OMAP USBOTG module has a requirement to set the autoidle bit only after setting smartidle bit. Modified the _sys_enable api to set the smartidle first and then the autoidle bit. Setting this will not have any impact on the other modules. Signed-off-by:
Hema HK <hemahk@ti.com> Signed-off-by:
Partha Basak <p-basak2@ti.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Acked-by:
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Rajendra Nayak authored
The omap4_cm_wait_module_ready function would only check for the modules to be completely functional before declaring them ready to be accessed. There might also be instances where in the module is actually in idle (under h/w control) but should still be declared accessible, as the h/w control would make it functional when needed. Hence make omap4_cm_wait_module_ready return true in case the module is fully functional *or* in idle state. Fail only if the module is fully disabled or stuck intransition. The explaination from the TRM for the idlest bits on OMAP4 is as below for quick reference Module idle state: 0x0 func: Module is fully functional, including OCP 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep abortion 0x2 idle: Module is in Idle mode (only OCP part). It is functional if using separate functional clock 0x3 disabled: Module is disabled and cannot be accessed Signed-off-by:
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