- Jul 17, 2018
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Fabio Estevam authored
There are two variants of imx6ul-pico boards: one with 256MB and another one with 512MB of RAM. Do not hardcode the memory size in the device tree and let the bootloader fill the correct value instead. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Robin Gong authored
On i.MX6SL EVK board, pfuze100 sw4 supplies LPDDR2 which is critical for system, must be always on. Signed-off-by:
Robin Gong <yibin.gong@nxp.com> Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
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Anson Huang authored
On i.MX6SLL EVK board, pfuze100 sw4 supplies LPDDR3 which is critical for system, must be always on. Signed-off-by:
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Anson Huang authored
On i.MX6SX SDB Rev-A board, pfuze100 sw4 supplies csi, audio codec and i2c etc., these modules do NOT implement power domain control, so pfuze100 sw4 needs to be always on to make sure these modules work normally. Signed-off-by:
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Anson Huang authored
On i.MX6QDL Sabre-SD board, pfuze100 sw4 supplies GPS, touch and RGMII etc., these modules do NOT implement power domain control, so pfuze100 sw4 needs to be always on to make sure these modules work normally. Signed-off-by:
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Anson Huang authored
On i.MX6SL EVK board, the MX6SL_PAD_KEY_ROW5 pin is used as lcd 3v3 regulator control pin, need to make sure MX6SL_PAD_KEY_ROW5 is muxed as GPIO function for controlling lcd 3v3 regulator. Signed-off-by:
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Andrey Smirnov authored
It looks like I made a nasty typo in the original patch which resulted in missing watchdog device. Fix it. Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: cphealy@gmail.com Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by:
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Andrey Smirnov authored
Instead of relying on default values, configure PAD_AUD3_BB_CK to be a GPIO explicitly. While at, it change the pad configuration to enable a 100K pull-down (the pin is used as IRQ_TYPE_LEVEL_HIGH). Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: cphealy@gmail.com Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn <andrew@lunn.ch> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Gary Bisson authored
This display configuration isn't working as-is as it depends on the tfp410 LCD to HDMI bridge. This will need to be updated later once the DRM MXSFB driver will be the default. Signed-off-by:
Gary Bisson <gary.bisson@boundarydevices.com> Reviewed-by:
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Gary Bisson authored
To make use of the new eLCDIF DRM driver OF graph description is required. Describe the display using OF graph nodes. Signed-off-by:
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Gary Bisson authored
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by:
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Leonard Crestez authored
The imx6sl soc has gpu_2d and gpu_vg, no 3d support: etnaviv-gpu 2200000.gpu: model: GC320, revision: 5007 etnaviv-gpu 2204000.gpu: model: GC355, revision: 1215 The IP blocks seem to be already supported. Signed-off-by:
Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
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Anson Huang authored
Enable SEIKO 43WVF1G lcdif panel for DRM driver, add necessary properties according to SEIKO 43WVF1G driver's requirement, such as "dvdd-supply", "avdd-supply" and "backlight" etc.. Signed-off-by:
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Anson Huang authored
On i.MX6SLL EVK board, lcd regulator is controlled by GPIO4 IO03 using MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 pin, NOT MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08, correct it. Signed-off-by:
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Anson Huang authored
Enable pwm1 module on i.MX6SLL EVK board to make backlight driver really work with LCD panel connected. Signed-off-by:
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Fabio Estevam authored
Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by:
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Fabio Estevam authored
Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by:
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Sebastian Reichel authored
Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.co.uk> [fabio: kept the change only in imx53-ppd context] Signed-off-by:
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Alex Gonzalez authored
The ConnectCore 6UL Single Board Computer (SBC) Express contains the ConnectCore 6UL System-On-Module. Its hardware specifications are: * 256MB DDR3 memory * 256MB NAND flash * Single Ethernet * USB Host and USB-OTG * MicroSD external storage * Groove connectors and Raspberry Pi Hat compatible expansion header Signed-off-by:
Alex Gonzalez <alex.gonzalez@digi.com> Signed-off-by:
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Alex Gonzalez authored
The ConnectCore 6UL System-On-Module has the following hardware specification: * Based on a NXP i.MX6UL SoC * Industrial temperature ranges (-40ºC to +85ºC) * Up to 1GB DDR3 memory * Up to 2GB NAND flash * Dual Ethernet * On module 802.11 WiFi and Bluetooth 4.2 (QCA6564) * On module NXP Kinetis KL03 * On module Microchip ATECC508A crypto element Signed-off-by:
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Fabio Estevam authored
imx51-zii-rdu1 has an external watchdog in the environment microcontroller, so disable the internal one. This aligns with what was done in commit 7055f714 ("ARM: dts: imx6: RDU2: disable internal watchdog") for imx6 rdu2 board. Signed-off-by:
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- Jul 12, 2018
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Fabio Estevam authored
Add a label for the PMU node so that the board dts may be able to pass the 'secure-reg-access' property like this: &pmu { secure-reg-access; }; This also makes it consistent with the PMU node in imx6qdl.dtsi Signed-off-by: -
Fabio Estevam authored
As per the i.MX53 Reference Manual add an entry for the 'tigerp' region in the device tree. This is needed for accessing the ARM_GPC register to set the DBGEN bit, so that the debug clocks can be turned on. Signed-off-by:
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Fabio Estevam authored
As per the i.MX51 Reference Manual add an entry for the 'tigerp' region in the device tree. This is needed for accessing the ARM_GPC register to set the DBGEN bit, so that the debug clocks can be turned on. Signed-off-by:
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Fabio Estevam authored
Add PMU support in the device tree. Signed-off-by:
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Fabio Estevam authored
Add bindings for the tigerp module present on i.MX51. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Fabio Estevam authored
As per the i.MX51 Reference Manual the M4IF register region starts at 0x83fd8000 and has a 4kB address range. Add support for it. Signed-off-by:
Sergey Lapin <sergey.lapin@cogentembedded.com> Reviewed-by:
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Fabio Estevam authored
Add bindings for the M4IF module present on i.MX51. Signed-off-by:
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- Jul 11, 2018
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Andrey Smirnov authored
Add support for the Zodiac Inflight Innovations i.MX51-base SCU3 Ethernet Switch Board (ESB) Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: cphealy@gmail.com Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by:
Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by:
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Leonard Crestez authored
With old bindings imx_gpc_onecell_data always sets num_domains to 2 so the DISPMIX domain can't actually be referenced. The pd is still defined and pm core shuts it down as "unused" so display can't work. Fix this by converting to new gpc bindings by adding pgc nodes and referencing the newly-defined &pu_disp domain from &lcdif. Signed-off-by:
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Anson Huang authored
i.MX6SX has a 16KB always-on ocram bank called ocram_s, enable it as another mmio sram. Signed-off-by:
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Stefan Agner authored
100/200MHz states for USDHC3 are not required since the SoC does not support modes faster than DDR52 for the on board eMMC. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Stefan Agner authored
VDDD is connected to VGEN4 of the PF0100. This rail should only run at 1.8V since there are multiple consumer and they all expect the rail to be at 1.8V. Signed-off-by:
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Stefan Agner authored
Remove the 2.5V regulator, it does not exist. There is 3.3V and 3.3V_AUDIO provided to the module through the edge connector, model those as fixed regulators like we use to do in other Colibri device trees. The SGTL5000 uses 3.3V_AUDIO as VDDA. Note that the driver derives the analog ground voltage (VAG) from this supply. The new value should allow higher output swings before clipping occurs. Refer to the SGTL5000 datasheet for details. Signed-off-by:
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Stefan Agner authored
The fixed 1.8V regulator is not used, and there is in fact no fixed 1.8V regulator on the module. Remove it. Signed-off-by:
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Stefan Agner authored
Use the disable-wp to indicate that Apalis and Colibri iMX6 do not make use of the native write-protect signal available on the i.MX 6 SoCs. This prevents warnings: mmc0: host does not support reading read-only switch, assuming write-enable Signed-off-by:
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Stefan Agner authored
Use no-1-8-v device tree property to indicate that the board does not support 1.8V signaling. The property voltage-ranges seems not appropriate in our case since we do not have level shifters in place. Signed-off-by:
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Stefan Agner authored
Add the 3.3V main supply on the carrier board. Currently as a fixed supply since not all consumer are modeled yet. This gets also rid of some missing supply warnings. Signed-off-by:
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Stefan Agner authored
Add Apalis UART1 as default serial console. Signed-off-by:
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Andrey Smirnov authored
Add support for the Zodiac Inflight Innovations SCU2 Mezz board (i.MX51-based). Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: cphealy@gmail.com Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by:
Chris Healy <cphealy@gmail.com> Signed-off-by:
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