- Mar 19, 2020
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Yintian Tao authored
Originally, only the PTE valid is taken in consider. The PRT case is missied when bo update which raise problem. We need add condition for PRT case. v2: add PRT condition for amdgpu_vm_bo_update_mapping, too v3: fix one typo error Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
Adds logic that will determine if pipes need merging during validation. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Wyatt Wood authored
[Why] The scratch space can be used to pass data between x86 and DMCUB. DMCUB will manage the actually mapping of CW7 internally, driver does not program the window. [How] Allocate extra space within the DMUB service's framebuffer for this scratch space and expose them from the service for use in DC. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] before update dpp DTO, we check dppclks in context to determine it is changed or not, but dppclks in context will be updated anyways after flip is done, so compare dppclks in context will always get an equal result. [How] Add pipe dpp clks in dccg and compare values between dccg and context. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] Causes regression with MST DSC displays not lighting up after DPMS [how] Revert commit 8cc426d7 ("drm/amd/display: Program DSC during timing programming") Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] underflow happened when playing video on 1366x768 + 4K clone mode due to incorrect handle watermark change flag and lower down clocks to early. [How] Check watermark change flag when decide doing optimized, and check optimized required flag to do clock update. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Charlene Liu authored
[why] this register not exist in some asic, based on request remove this from dc. [how] add guard for sanization. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Martin Tsai authored
[Why] We should check MST BU support capability on output port before building vsc info packet. [How] Add a new definition for port and sink capability check. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Sung Lee authored
[WHY] In headless boot cases, self refresh control registers are not programmed on boot. In certain hybrid graphics cases this may cause cstate entering to get blocked causing a hang. [HOW] Program self refresh control register on boot. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Wenjing Liu authored
[why] DP doesn't have message id as the first byte of an hdcp message, current hdcp psp unifies HDMI and DP message so that it is required when reading DP HDCP messages in hdcp_ddc, a message id needs to be added as the first byte of the HDCP message. The id is currently assigned as a magic number which is not a good coding practice. [how] Replace magic numbers with macro defined in hdcp headers. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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Wyatt Wood authored
[Why] We want to be able to enable/disable psr on dmcub and fallback to dmcu when necessary. [How] Use dc config option to do so. Signed-off-by:
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Wyatt Wood authored
[Why] The default value for disable_dmcu is true, even for asics that require dmcu. [How] Set flag properly per asic. Signed-off-by:
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Roman Li authored
[Why] The PSR enablement was dependent on swizzle as a workaround for non-pageflipping fb console. It's no longer required. [How] Remove PSR-enable dependency on swizzle mode. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] This is enabled by default on Renoir but there's userspace/API support to actually make use of this. Since we're not passing this down through surface updates, let's explicitly disable this for now. This fixes "dcn20_program_front_end_for_ctx" warnings associated with incorrect/unexpected programming sequences performed while this is enabled. [How] Disable it at the topmost level in DM in case anyone tries to flip this to enabled for any of the other ASICs like Navi10/14. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] A "dcn20_program_front_end_for_ctx" warning is observed on Renoir. Since the resource definition doesn't explicitly disable triplebuffer flips like Navi10 DC actually attempts to go and setup triplebuffering even when we pass in false to the plane state. If we hit a full update after triplebuffering has been setup we see the assertion since we don't expect full updates while performing triplebuffer flips. Normally this would get reset back to false whne we pass in the new plane state, but since we never actually copy the flag when doing surface updates this doesn't happen. [How] Copy the flag onto the plane update based on the requested surface update state. Signed-off-by:
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Dmytro Laktyushkin authored
Right now only stream count is used to avoid split. This change updates the W/A to check plane count instead. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] When hotplug a HDMI monitor during entering S0i3 or DPMSOFF state due to entering infinite loop when calling vbios to program pixel clocks. In this scenario, pll is enabled but phy is not, and there is not a programing guide for this case. [How] Before we having the proper programing guide, before disable pll, doing a phy enable and disable to avoid the issue. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Isabel Zhang authored
[Why] Due to previous code changes displays which are in active state immediately transition to the active and added state. This makes the two states redundant and unnecessary. [How] Instead of updating the device state to active and added after successful addition, change state to inactive if addition failed. Also, change references to active and added state to just added state. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
[why] When reprogram MSA with updated color space, the test color space shows inconsistency. Linux has separate routine to set up test pattern color space, but it fails to configure RGB. [How] Add RGB to test pattern. Fixes: 43563bc2 ("drm/amd/display: update MSA and VSC SDP on video test pattern request") Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Hersen Wu authored
[Why] drm_connector->display_info is not passed to amdgpu_dm right way after read edid. [How] display_info is parsed from edid and saved into drm_connector by drm_connector_update_edid_proerty which is called within amdgpu_dm_update_connector_after_detect. call this function after read edid to update drm_connector->display_info Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Sung Lee authored
[WHY] Not programming dto with same values causes test failures in DCN2 diags DPP tests. [HOW] This reverts commit 1b53e733. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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- Mar 16, 2020
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Nirmoy Das authored
VCN HW doesn't support dynamic load balance on multiple instances for a context. This patch initializes VNC entities with only one drm_gpu_scheduler picked by drm_sched_pick_best(). Picking a drm_gpu_scheduler using drm_sched_pick_best() ensures that we do load balance among multiple contexts but not among multiple jobs in a context. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Nirmoy Das authored
Remove drm_sched_entity_get_free_sched() and use the logic of picking the least loaded drm scheduler from a drm scheduler list to implement drm_sched_pick_best(). This patch also exports drm_sched_pick_best() so that it can be utilized by other drm drivers. Signed-off-by:
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changzhu authored
It needs to revert this patch to avoid amdgpu_test compute hang problem on picasso. This reverts commit 56822db1. Signed-off-by:
changzhu <Changfeng.Zhu@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Puts the i2c adapter in common place for sharing by RAS and upcoming data read from FRU EEPROM feature. v2: Move i2c adapter to amdgpu_pm and rename it. v3: Move i2c adapter init to ASIC specific code and get rid of the switch case in amdgpu_device Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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xinhui pan authored
Job fence on page table should be a shared one, so add it to the root page talbe bo resv. last_delayed field is not needed anymore. so remove it. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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Nirmoy Das authored
Fix switch-case indentation in amdgpu_ctx_init_entity() Signed-off-by:
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Monk Liu authored
what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can access reg that need RLCG path help now even debugfs's reg_op can used to dump wave. tested-by:
Monk Liu <monk.liu@amd.com> tested-by:
Zhou pengju <pengju.zhou@amd.com> Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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- Mar 13, 2020
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Lucas Stach authored
1db8c142 (drm/scheduler: Add drm_sched_suspend/resume_timeout()) made the job_list_lock IRQ safe in as the suspend/resume calls were expected to be called from IRQ context. This usage never materialized in upstream. Instead amdgpu started locking the job_list_lock in an IRQ unsafe way in amdgpu_ib_preempt_mark_partial_job() and amdgpu_ib_preempt_job_recovery(), which leads to potential deadlock if one would actually start to call the drm_sched_suspend/resume_timeout functions from IRQ context. As no current user needs the locking to be IRQ safe, the local IRQ disable/enable is pure overhead. Fix the inconsistent locking by changing all uses of job_list_lock to use the IRQ unsafe locking primitives. Reviewed-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
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Robert Beckett authored
Add a new trace event to show when jobs are run on the HW. Acked-by:
Robert Beckett <bob.beckett@collabora.com> Signed-off-by:
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Kevin Wang authored
clean up unused header in swsmu driver stack: 1. pp_debug.h 2. amd_pcie.h 3. soc15_common.h Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Dennis Li authored
AccVGPRs are newly added in arcturus. Before reading these registers, they should be initialized. Otherwise edc error happens, when RAS is enabled. v2: reuse the existing logical to calculate register size Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Mario Kleiner authored
This fixes a problem found on the MacBookPro 2017 Retina panel: The panel reports 10 bpc color depth in its EDID, and the firmware chooses link settings at boot which support enough bandwidth for 10 bpc (324000 kbit/sec aka LINK_RATE_RBR2 aka 0xc), but the DP_MAX_LINK_RATE dpcd register only reports 2.7 Gbps (multiplier value 0xa) as possible, in direct contradiction of what the firmware successfully set up. This restricts the panel to 8 bpc, not providing the full color depth of the panel on Linux <= 5.5. Additionally, commit '4a8ca46b ("drm/amd/display: Default max bpc to 16 for eDP")' introduced into Linux 5.6-rc1 will unclamp panel depth to its full 10 bpc, thereby requiring a eDP bandwidth for all modes that exceeds the bandwidth available and causes all modes to fail validation -> No modes for the laptop panel -> failure to set any mode -> Panel goes dark. This patch adds a quirk specific to the MBP 2017 15" Retina panel to override reported max link rate to the correct maximum of 0xc = LINK_RATE_RBR2 to fix the darkness and reduced display precision. Please apply for Linux 5.6+ to avoid regressing Apple MBP panel support. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
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Lyude Paul authored
These are some very loud debug statements that get printed on every vblank when driver level debug printing is enabled in DRM, and doesn't really tell us anything that isn't related to vblanks. So let's move this over to the proper debug flag to be a little less spammy with our debug output. Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Dan Carpenter authored
If "speed" is zero then we use it as a divisor to find "prescale". It's better to move the check for zero to the very start of the function. Fixes: 9eeec26a ("drm/amd/display: Refine i2c frequency calculating sequence") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Dan Carpenter authored
These lines were accidentally indented 4 spaces more than they should be. Signed-off-by:
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Dan Carpenter authored
We can remove the NULL check for "res_ctx" and "res_ctx->pipe_ctx[i].stream->link". Also it's nicer to align the conditions using spaces so I re-indented a bit. Longer explanation: The "res_ctx" pointer points to an address in the middle of a struct so it can't be NULL. For "res_ctx->pipe_ctx[i].stream->link" we know that it is equal to "link" and "link" is non-NULL. Signed-off-by:
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Randy Dunlap authored
Fix the Kconfig dependencies so that the menu is presented correctly by adding a dependency on DRM_AMDGPU to the "menu" Kconfig statement. This makes a continuous dependency on DRM_AMDGPU in the DRM AMD menus and eliminates a broken menu structure. Fixes: a8fe58ce ("drm/amd: add ACP driver support") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: David (ChunMing) Zhou <David1.Zhou@amd.com> Cc: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Cc: amd-gfx@lists.freedesktop.org Signed-off-by:
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Joe Perches authored
Convert the various uses of fallthrough comments to fallthrough; Done via script Link: https://lore.kernel.org/lkml/b56602fcf79f849e733e7b521bb0e17895d390fa.1582230379.git.joe@perches.com/ Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Joe Perches authored
The automated conversion of /* fallthrough */ comments converted a comment outside of an #ifdef/#endif case block that should be inside the block. Move the fallthrough inside the block to silence the warning. Signed-off-by:
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