Commits · 35dc3f97a69bb344768c6a2f47da2be46b11645a · jan.koester / Linux · GitLab

Nov 18, 2015
- drm/i915: Give names to more ring registers · 35dc3f97
  Ville Syrjälä authored Nov 04, 2015
  35dc3f97
- drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0) · 9244a817
  Ville Syrjälä authored Nov 04, 2015
  9244a817
- drm/i915: Add wa_ctx_emit_reg() · 8f40db77
  Ville Syrjälä authored Nov 04, 2015
  8f40db77
- drm/i915: Add functions to emit register offsets to the ring · f92a9162
  Ville Syrjälä authored Nov 04, 2015
  f92a9162
- drm/i915: Make the cmd parser 64bit regs explicit · e597ef40
  Ville Syrjälä authored Nov 06, 2015
  e597ef40
- drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl · 8697600b
  Ville Syrjälä authored Nov 06, 2015
  8697600b
- drm/i915: s/0x50/RING_PSMI_CTL/ · 3613cf1d
  Ville Syrjälä authored Nov 04, 2015
  3613cf1d
- drm/i915: Parametrize MOCS registers · e6c4c763
  Ville Syrjälä authored Nov 05, 2015
  e6c4c763
- drm/i915: Parametrize L3 error registers · 6fa1c5f1
  Ville Syrjälä authored Nov 04, 2015
  6fa1c5f1
- drm/i915: Prefix raw register defines with underscore · 086f8e84
  Ville Syrjälä authored Nov 04, 2015
  086f8e84
- drm/i915: Streamline gpio_mmio_base deduction · b2e8c6cd
  Ville Syrjälä authored Nov 04, 2015
  b2e8c6cd
- drm/i915: Store DVO SRCDIM register offset under intel_dvo_device · 78e0d2e3
  Ville Syrjälä authored Nov 04, 2015
  78e0d2e3
- drm/i915: s/is_sdvob/enum port/ · 2a5c0832
  Ville Syrjälä authored Nov 06, 2015
  2a5c0832
- drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to its only user · c48b5305
  Ville Syrjälä authored Nov 04, 2015
  c48b5305
- pci: Decouple quirks.c from i915_reg.h · aba72ddc
  Ville Syrjälä authored Nov 04, 2015
  aba72ddc
- drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_priv. · 6d8175da
  Rodrigo Vivi authored Nov 05, 2015
  6d8175da
- drm/i915: Stop tracking last calculated Sink CRC. · 7e38eeff
  Rodrigo Vivi authored Nov 05, 2015
  7e38eeff
- drm/i915: Make Sink crc calculation waiting for counter to reset. · c6297843
  Rodrigo Vivi authored Nov 05, 2015
  c6297843
- drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop. · d72f9d91
  Rodrigo Vivi authored Nov 05, 2015
  d72f9d91
Nov 17, 2015
- drm/i915/skl: Remove unused suspend and resume callbacks · a03bc7cd
  Patrik Jakobsson authored Nov 09, 2015
  a03bc7cd
- drm/i915/gen9: Add boot parameter for disabling DC6 · 443646c7
  Patrik Jakobsson authored Nov 16, 2015
  443646c7
- drm/i915/gen9: Turn DC handling into a power well · 9f836f90
  Patrik Jakobsson authored Nov 16, 2015
  9f836f90
- drm/i915: Explain usage of power well IDs vs bit groups · cd02ac52
  Patrik Jakobsson authored Nov 16, 2015
  cd02ac52
- drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5() · b450e177
  Patrik Jakobsson authored Nov 09, 2015
  b450e177
- drm/i915: Add a modeset power domain · dfa57627
  Patrik Jakobsson authored Nov 09, 2015
  dfa57627
- drm/i915: Remove distinction between DDI 2 vs 4 lanes · 6331a704
  Patrik Jakobsson authored Nov 09, 2015
  6331a704
- drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS · edd993fd
  Ville Syrjälä authored Nov 09, 2015
  edd993fd
- drm/i915: Introduce a gmbus power domain · f0ab43e6
  Ville Syrjälä authored Nov 09, 2015
  f0ab43e6
- drm/i915: Clean up AUX power domain handling · 25f78f58
  Ville Syrjälä authored Nov 16, 2015
  25f78f58
- drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6 · 4deccbb2
  Patrik Jakobsson authored Nov 09, 2015
  4deccbb2
- drm/i915: Don't trust CSR program memory contents · fc131bf2
  Patrik Jakobsson authored Nov 09, 2015
  fc131bf2
- drm/i915: fix handling of the disable_power_well module option · d314cd43
  Imre Deak authored Nov 17, 2015
  d314cd43
- drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enabling · c2b16152
  Imre Deak authored Nov 04, 2015
  c2b16152
- drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLK · ab96c1ee
  Imre Deak authored Nov 04, 2015
  ab96c1ee
- drm/i915/skl: disable DC states before display core init/uninit · d26fa1d5
  Imre Deak authored Nov 04, 2015
  d26fa1d5
- drm/i915/gen9: simplify DC toggling code · 13ae3a0d
  Imre Deak authored Nov 04, 2015
  13ae3a0d
- drm/i915/skl: don't toggle PW1 and MISC power wells on-demand · 4a76f295
  Imre Deak authored Nov 04, 2015
  4a76f295
- drm/i915/skl: init/uninit display core as part of the HW power domain state · 73dfc227
  Imre Deak authored Nov 17, 2015
  73dfc227
- drm/i915: rename intel_power_domains_resume to *_sync_hw · 30eade12
  Imre Deak authored Nov 04, 2015
  30eade12
- drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences · 2f693e28
  Damien Lespiau authored Nov 04, 2015
  2f693e28