- Oct 22, 2015
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Chen-Yu Tsai authored
The cubieboard uses the internal codec to output sound to its mini-jack. Enable it. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
The CHIP v0.2 has a composite output on a mini-jack connector, the audio part being provided by the on-SoC codec. Enable it. Signed-off-by:
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Marcus Cooper authored
Enable the audio-codec on the Mele A1000 top-set box. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> Signed-off-by:
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Maxime Ripard authored
The cubieboard2 uses the internal codec to output sound to its mini-jack. Enable it. Signed-off-by:
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Emilio López authored
This commit enables the on-chip audio codec present on the A20 SoC for the Cubietruck. Signed-off-by:
Emilio López <emilio@elopez.com.ar> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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- Oct 21, 2015
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Emilio López authored
The A20 SoC includes the Allwinner audio codec, capable of both 24-bit playback and capture. This commit adds a device node for it. Signed-off-by:
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Maxime Ripard authored
The A13 and A10s also have the audio codec present. List it in the device tree. Signed-off-by:
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Marcus Cooper authored
The A10 SoC includes the Allwinner audio codec, capable of both 24-bit playback and capture. This commit adds a device node for it. Signed-off-by:
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Maxime Ripard authored
The audio codec functional clock is a child of PLL2 and is used to control the audio rate, enable it in the DT. Signed-off-by:
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Maxime Ripard authored
The audio codec functional clock is a child of PLL2 and is used to control the audio rate, enable it in the DT. Signed-off-by:
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Maxime Ripard authored
The audio codec functional clock is a child of PLL2 and is used to control the audio rate, enable it in the DT. Signed-off-by:
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Maxime Ripard authored
The A20 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI. Signed-off-by:
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Maxime Ripard authored
The A13 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). However, it has a different divider configuration than the A10, hence the difference compatible. Signed-off-by:
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Maxime Ripard authored
The A10 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI. Signed-off-by:
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- Oct 19, 2015
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Adam Sampson authored
The OTG arrangement on the LinkSprite pcDuino v3 Nano is the same as the pcDuino 1/2/3: the OTG port's 5V line is connected directly to the 5V bus (it's not switchable), and the OTG port's ID pin is connected to PH4 on the A20. Tested successfully in both host and device modes. Signed-off-by:
Adam Sampson <ats@offog.org> Acked-by:
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Chen-Yu Tsai authored
The Sinlinx A31s SDK is a A31s based module/baseboard development kit. The core module has the SoC, PMIC, DRAM, eMMC and supporting components. There are also pads for UART0, JTAG and I2S. The baseboard has 100 Mbps Ethernet, 5x USB 2.0 host ports via a USB 2.0 hub chip, MMC, HDMI, SPDIF, CIR, audio jacks, 2 tablet-like volume buttons, RS232 style UART and USB OTG (though VBUS is not connected). Various headers are available for other addon modules, such as SDIO WiFi, LCD display, camera sensor, UARTs, I2C, SPI and GPIOs. Signed-off-by:
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- Oct 17, 2015
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Hans de Goede authored
The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features 1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver, stereo headphone jack and hdmi video output. Signed-off-by:
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Hans de Goede authored
Add a pinmux setting for using mmc2 in regular 4 bit mode. Signed-off-by:
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Hans de Goede authored
When the gpio interrupt bindings where changed to add a bank to the specifier list, the r_pio nodes of A23/A31/A33 where not updated to match and neither was the pio node of the A80, this fixes this. Signed-off-by:
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- Oct 16, 2015
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Chen-Yu Tsai authored
The NMI interrupt controller is in charge of the NMI pin exposed by the SoC to the PMIC. The PMIC signals interrupts through this. Signed-off-by:
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- Oct 13, 2015
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Chen-Yu Tsai authored
The DC5LDO regulator supplies VDD-CPUS, which is for the embedded controller in the A31 SoC. Signed-off-by:
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Chen-Yu Tsai authored
Now that we have axp22x.dtsi describing common axp22x hardware, use it and reference the nodes instead of declaring the whole tree. Also drop the "always-on" from the vdd-gpu regulator, since we don't support the GPU anyway. And add a regulator reference for cpu0. Signed-off-by:
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Chen-Yu Tsai authored
The VDD-CPU and VDD-GPU regulators were incorrectly swapped. Fixes: bab03561 ("ARM: dts: sun6i: hummingbird: Add AXP221 regulator nodes") Signed-off-by:
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Adam Sampson authored
The power configuration on this board is the same as the pcDuino v3. This will enable frequency/voltage scaling over the standard A20 operating points from 144 MHz to 960 MHz. Tested using cpufreq-ljt-stress-test on two pcDuino v3 Nano boards; also tested successfully with voltages reduced by 0.025 V. Signed-off-by:
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Hans de Goede authored
We've everything we need to support the gmac on Colombus, turn it on. Signed-off-by:
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Hans de Goede authored
A33 Q8 tablets with the et-q8-v1.6 pcb will work fine with the generic q8-tablet.dts and given the many variants of PCBs found in Q8 tablets using such a specific dts name was a mistake in hindsight. We cannot just drop the et-q8-v1.6.dtb as existing u-boot configs may very well point to it. Signed-off-by:
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Hans de Goede authored
A23 Q8 tablets with the ippo-q8h-v* pcb will work fine with the generic q8-tablet.dts and given the many variants of PCBs found in Q8 tablets using such a specific dts name was a mistake in hindsight. We cannot just drop the ippo-q8h-v*.dtb as existing u-boot configs may very well point to it. Signed-off-by:
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Hans de Goede authored
This is a generic dts file for A23 based q8 formfactor tablets, this is intended to replace both sun8i-a23-ippo-q8h-v5.dts and sun8i-a23-ippo-q8h-v1.2.dts (these can be fully dropped after a transition period). Signed-off-by:
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- Oct 12, 2015
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Hans de Goede authored
All A13 based q8 formfactor tablets use the same backlight setup, add a backlight devicetree node for controlling the backlight on these devices. Signed-off-by:
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Chen-Yu Tsai authored
Q8 format tablets use channel 0 of the PWM controller for backlight dimming. Signed-off-by:
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Hans de Goede authored
Add a pinmux setting for the first pwm channel. This is often used for backlight dimming on tablets. Signed-off-by:
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Hans de Goede authored
Add dts nodes for the PWM controller on the A13 / A10s. Signed-off-by:
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Maxime Ripard authored
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack and two connectors to plug additional boards on top of it. Signed-off-by:
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Chen-Yu Tsai authored
The AXP22x family of PMIC is used with some Allwinner SoCs. This includes the AXP221, AXP221s and AXP223. They differ in the host interface, maximum supply current for DCDC1 regulator, and default voltage and state for various LDO regulators. Also, the AXP221s does not support fine calibration of the battery fuel gauge. This patch adds a dtsi file for all the common bindings for these PMICs. Currently this is just listing all the regulator nodes. The regulators are initialized based on their device node names. Signed-off-by:
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- Oct 11, 2015
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Adam Sampson authored
The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a single RT9701GB regulator, which has its enable input tied to the A20's PD2 pin, pulled up to 3v3 via a 10k resistor. However, the script.bin that shipped with the device listed PH11 and PH3 as Vbus control pins for the two USB ports. Neither of these are actually connected to anything. Siarhei Siamashka spotted this problem while reviewing the other LinkSprite boards. This patch fixes it by only defining a single regulator, controlled by PD2. Testing shows that the USB ports are now (correctly) only powered up once the USB PHY driver is loaded. Reported-by:
Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by:
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Maxime Ripard authored
Add a separate pinctrl node for the UART3 CTS and RTS pins shared between the A10s and A13. Signed-off-by:
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Maxime Ripard authored
The uart3 pins are shared between the A10s and A13, move the pinctrl node to the common DTSI to avoid duplication. Signed-off-by:
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Maxime Ripard authored
The R8 is very close to the A13, but it still has a few differences, notably a composite output, which the A13 lacks. Add a DTSI based on the A13's to hold those differences. Signed-off-by:
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Siarhei Siamashka authored
Enable the otg/drc usb controller on the pcDuino1/2 board. Note that the pcDuino1 FEX file from the vendor contains the following information in the [usbc0] section: usb_id_gpio = port:PH04<0><1><default><default> usb_det_vbus_gpio = port:PH05<0><0><default><default> usb_drv_vbus_gpio = port:PB09<1><0><default><0> While the pcDuino2 FEX has: usb_id_gpio = port:PH04<0><1><default><default> usb_det_vbus_gpio = port:PH05<0><0><default><default> usb_drv_vbus_gpio = port:PD02<1><0><default><0> The ID pin is indeed PH4. The PD2 pin can be used to switch power on/off for the USB Type A receptacle on pcDuino2, but it has nothing to do with the MicroUSB OTG receptacle. The VBUS pin of the MicroUSB receptacle is always connected to 5V according to the schematics (both pcDuino1 and pcDuino2) and confirmed by doing some tests on pcDuino2. The PH5 pin is just one of the pins on the J8 expansion header and has nothing to do with USB OTG. The PB9 pin is pulled up and connected to the N_VBUSEN pin of AXP209 PMIC, while the VBUS pin of AXP209 only has a capacitor between it and the ground (this pin is not used for anything else). To sum it up. Only the ID pin (PH4) has a real use. And 5V voltage is always served to the MicroUSB OTG receptacle no matter what is the state of the PB9/PD2 pins. This patch has been tested on pcDuino2 to work fine in a host role with a USB keyboard connected via an OTG cable. It also works fine in a device role (cdc_ether) with a regular Micro-B cable connected to a desktop PC. Signed-off-by: -
Siarhei Siamashka authored
The LinkSprite pcDuino2 board is almost identical to the older LinkSprite pcDuino1 board according to the schematic pdf files. So we just include the existing "sun4i-a10-pcduino.dts" file and make the necessary adjustments. Signed-off-by:
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