- Feb 23, 2015
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Magnus Damm authored
Sync the two DTS for the KZM9G board. The target is the file "sh73a0-kzm9g.dts" and it is made identical to the DT reference case with the exception of the compatbile string. In the future the DT reference file will go away. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> [geert: Update for recent changes to sh73a0-kzm9g-reference.dts] Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Define the generic R8A7794 parts of the SDHI[012] device nodes. Based on the orginal patch by Shinobu Uehara <shinobu.uehara.xc@renesas.com>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7790 device tree. Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7791 device tree. Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Define the Henninger board dependent part of the CAN0 device node. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Define the generic R8A7791 parts of the CAN0/1 device nodes. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Define the generic R8A7790 parts of the CAN0/1 device nodes. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Niklas Söderlund authored
Configure the pinmux on kzm9d to use the serial connector for uart1. Signed-off-by:
Niklas Söderlund <niso@kth.se> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Niklas Söderlund authored
With this information all GPIOs can make use of the PFC functionality. Signed-off-by:
Niklas Söderlund <niso@kth.se> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Add DT nodes for the ADV7511 HDMI encoder and its HDMI output connector and configure the DISP pin group that drives the HDMI transmitter DE pin. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Simon Horman authored
There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. Fixes: 59e79895 ("ARM: shmobile: r8a7791: Add clocks") Reported-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Simon Horman authored
* Correct base address of SD3 div6 clk. * Update div6 clock node labels There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. This has no run-time affect as the clock nodes are not currently used. Fixes: 8e181633 ("ARM: shmobile: r8a7794: Add SDHI clocks to device tree") Reported-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reported-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Laurent Pinchart authored
Enable the ethernet controller for the Alt board. Pin muxing entries are currently left out as r8a7794 pin control support isn't available yet. We thus rely on the boot loader to configure ethernet pins for now. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Add a DT node for the on-SoC ethernet controller device. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Add the six IPMMU instances found in the r8a7794 to DT with a disabled status. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Add the seven IPMMU instances found in the r8a7791 to DT with a disabled status. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Add the six IPMMU instances found in the r8a7790 to DT with a disabled status. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Instantiate the two system DMA controllers in the r8a7794 device tree. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Ulrich Hecht authored
Specifies clock sources and register bits. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> [geert: Drop renesas,src-shift/renesas,src-width, pad to 4 or 8 parents] Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
This clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Enable the kzm9g touchscreen controller in the board's DT file. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a DT node for the R2025D real-time clock, which is connected to i2c0. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a DT node for the ADXL345 three-axis digital accelerometer sensor, which is connected to i2c0. As trivial i2c devices are matched against the first compatible entry only, compatibility is declared with "adi,adxl34x" only for now. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> The device needs an interrupt to operate properly. Specify the two interrupts used on the board. While at it rename the DT node to accelerometer@1d to describe the device's function instead of its model. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a DT node for the AK8975 magnetometer sensor, which is connected to i2c0. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Specify the device interrupt to avoid polling for end of conversion. While at it rename the DT node to compass@c to describe the device's function instead of its model. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
While at it rename the ak4648 node to "codec" to describe the device's function instead of its model, and move its device-specific property after its generic properties. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
The sh73a0 INTC can't mask interrupts properly most likely due to a hardware bug. Set the control-parent property to delegate masking to the parent interrupt controller. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Ulrich Hecht authored
This adds the remaining DIV6 clocks and all possible parents for the SUB clock. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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- Feb 17, 2015
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Arnaud Ebalard authored
"isil" and "isl" prefixes are used at various locations inside the kernel to reference Intersil corporation. This patch is part of a series fixing those locations were "isl" is used in compatible strings to use the now expected "isil" prefix instead (NASDAQ symbol for Intersil and most used version). Note: isl9305 is an I2C device so the patch does not in fact currently depend on the introduction of "isil"-based compatible string in isl9305 driver (provided by another patch) because I2C core does not check the prefix yet. Signed-off-by:
Arnaud Ebalard <arno@natisbad.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Uwe Kleine-Knig <uwe@kleine-koenig.org> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Peter Huewe <peter.huewe@infineon.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Darshana Padmadas <darshanapadmadas@gmail.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Landley <rob@landley.net> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Uwe Kleine-König <uwe@kleine-koenig.org> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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- Feb 16, 2015
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Ray Jui authored
Add I2C device nodes and its properties in bcm-cygnus.dtsi but keep them disabled there. Individual I2C devices can be enabled in board specific dts file when I2C slave devices are enabled in the future Signed-off-by:
Ray Jui <rjui@broadcom.com> Reviewed-by:
Scott Branden <sbranden@broadcom.com> Reviewed-by:
Kevin Cernekee <cernekee@chromium.org> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli authored
The L2 cache properties were completely off with respect to what the hardware is configured for. Fix the cache-size, cache-line-size and cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways and 32 bytes per cache-line. Fixes: 46d4bca0 ("ARM: BCM63XX: add BCM63138 minimal Device Tree") Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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- Feb 14, 2015
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Gregory CLEMENT authored
The Marvell Armada 38x SoCs contains an RTC which differs from the RTC used in the other mvebu SoCs until now. This commit adds the Device Tree description of this interface at the SoC level. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Arnaud Ebalard <arno@natisbad.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Boris BREZILLON <boris.brezillon@free-electrons.com> Cc: Lior Amsalem <alior@marvell.com> Cc: Tawfik Bayouk <tawfik@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Arnaud Ebalard authored
Now that alarm support for ISL12057 chip is available w/ the specific "isil,irq2-can-wakeup-machine" property, let's use that feature of the driver dedicated to NETGEAR ReadyNAS 102, 104 and 2120 specific routing of RTC Alarm IRQ#2 pin; on those devices, this pin is not connected to the SoC but to a PMIC, which allows the device to be powered up when RTC alarm rings. For that to work, the chip needs to be explicitly marked as a device wakeup source using this "isil,irq2-can-wakeup-machine" boolean property. This makes 'wakealarm' sysfs entry available to configure the alarm. Signed-off-by:
Arnaud Ebalard <arno@natisbad.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Peter Huewe <peter.huewe@infineon.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Thierry Reding <treding@nvidia.com> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Darshana Padmadas <darshanapadmadas@gmail.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Landley <rob@landley.net> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Kumar Gala <galak@codeaurora.org> Cc: Uwe Kleine-König <uwe@kleine-koenig.org> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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- Feb 09, 2015
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Sylwester Nawrocki authored
Now when the CDCLK I2S output clock can be handled through the clock API the Odroid X2/U3 can be switched to the simple-audio-card DT binding. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Sylwester Nawrocki authored
Clock related properties are added to the Exynos4 I2S device nodes so they can be referred to as clock providers. Missing i2s_opclk1 clock is added to the I2S0 node and clock properties are added to the MAX98090 codec node to allow it to control/read frequency of the MCLK clock directly. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Feb 05, 2015
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Sylwester Nawrocki authored
I2S1, I2S2 on Exynos4 SoC series have limited functionality compared to I2S0, "samsung,s3c6410-i2s" compatible should be used for them. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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Andy Shevchenko authored
Instead of using magic number in the code the patch provides DW_DMA_MAX_NR_MASTERS constant. While here, restrict the reading of data width array by amount of the actual number of AHB masters. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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