- May 17, 2013
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Jean-Christophe PLAGNIOL-VILLARD authored
to prepare the switch to the macro. Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- May 09, 2013
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Doug Anderson authored
The 'samsung,vbus-gpio' was submitted before pinmux landed for exynos5250 and uses the old-style gpio specifier. Fix the two exynos5250 boards that use it. Signed-off-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Trivial patch, adding the i2c Cypress trackpad used on Snow. Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Jason Cooper authored
If a board isn't using twl4030, then dtc will complain about the missing phandle (which is in twl4030.dtsi). Move the phy declaration to the dts files. Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
The bootloader configures the pins, but has pull bits set without pull enable bits. While this is harmless, and won't do anything, it seems to cause confusion at least for me every time looking at the pin configuration. Fix it for DT based boot. Signed-off-by: -
Philip Avinash authored
Add GPMC data node to AM33XX device tree file. Signed-off-by:
Philip Avinash <avinashphilip@ti.com> Acked-by:
Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by:
Pekon Gupta <pekon@ti.com> Signed-off-by:
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Nishanth Menon authored
commit d16fb25d (ARM: dts: OMAP4460: Add CPU OPP table) introduced wrong OPP voltages per OPP by mistake. Sync the OPP tables with existing OMAP4460 OPP data in arch/arm/mach-omap2/opp4xxx_data.c Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
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Nishanth Menon authored
commit 3027e267 (ARM: dts: OMAP36xx: Add CPU OPP table) introduced wrong OPP voltages per OPP by mistake. Sync the OPP tables with existing OMAP36xx OPP data in arch/arm/mach-omap2/opp3xxx_data.c Signed-off-by:
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- May 08, 2013
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Jon Hunter authored
Commit ff5c9059 (ARM: dts: OMAP3+: Correct gpio #interrupts-cells property) updated the number of interrupt cells required for configuring gpios as interrupts for other devices (such as ethernet controllers). This update allowed the interrupt type (edge, level, etc) to be configured via device-tree (as described in the Documentation/devicetree/bindings/gpio/gpio-omap.txt). This broke ethernet support on the OMAP4 SDP board that defines a gpio as the ethernet IRQ because the interrupt type (level, edge, etc) was not getting configured correctly. This board use the ks8851 ethernet chip which has an active low interrupt. Fix this by defining the gpio interrupt as active-low in the device-tree binding. Please note that the OMAP4-VAR-SOM also uses the same ethernet controller and it is expected it will have the same problem. So the same fix is also applied to this board. Signed-off-by:
Jon Hunter <jon-hunter@ti.com> Signed-off-by:
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- Apr 29, 2013
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Olof Johansson authored
I fumbled when resolving a merge conflict on application of commit 765d012c (ARM: dts: exynos4210: Add basic dts file for universal_c210 board), and left out the dts source file. Here it is. Signed-off-by:
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- Apr 28, 2013
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Tomasz Figa authored
This patch adds basic device tree sources for Universal C210 board. Currently support includes: - eMMC - serial - max8952 and max8998 voltage regulators. - gpio-keys More support will be added in further patches. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
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Tomasz Figa authored
This patch adds device tree node for PWM block present on Exynos 4 SoCs. Signed-off-by:
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Olof Johansson authored
Add basic EC information to device tree, currently only describing the keyboard and keymap. Reviewed-by:
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Doug Anderson authored
Now that we have i2c-arbitrator in place on bus 4 we can add the sbs-battery driver. Future devices will be added onto bus 4 once drivers are in good shape. Signed-off-by:
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Doug Anderson authored
We need to use the i2c-arbitrator to talk to any of the devices on i2c bus 4 on exynos5250-snow so that we don't confuse the embedded controller (EC). Add the i2c-arbitrator to the device tree. As we add future devices (keyboard, sbs, tps65090) we'll add them on top of this. The arbitrated bus is numbered 104 simply as a convenience to make it easier for people poking around to guess that it might have something to do with the physical bus 4. The addition is split between the cros5250-common and the snow device tree file since not all cros5250-class devices use arbitration. Signed-off-by:
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- Apr 27, 2013
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Thomas Abraham authored
Commit 800974ac ("ARM: dts: Add board dts file for ODROID-X") includes a node to describe the board level properties for mshc controller. But the mshc controller node was not added in the Exynos4x12 dtsi file which resulted in the following warning when compiling the dtb files. Warning (reg_format): "reg" property in /mshc@12550000/slot@0 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /mshc@12550000/slot@0 Warning (avoid_default_addr_size): Relying on default #size-cells value for /mshc@12550000/slot@0 Fix this by adding the mshc controller node for Exynos4x12 SoCs. Signed-off-by:
Thomas Abraham <thomas.abraham@linaro.org> Tested-by:
Dongjin Kim <tobetter@gmail.com> Signed-off-by:
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Doug Anderson authored
This change makes the rtc on the exynos5250 and 5440 disabled by default to match exynos4. Ever since the common clock framework came in, exynos5250 boards have dumped lots of warnings in the boot log. It turns out that we don't see those on exynos4 since the rtc is disabled by default. While we need to get to the bottom of the problems with the RTC, it still makes sense to have the default state of the RTC on exynos boards match. For the record, warnings look like this: ------------[ cut here ]------------ WARNING: at drivers/clk/clk.c:771 __clk_enable+0x34/0xb0() Modules linked in: [<80015bfc>] (unwind_backtrace+0x0/0xec) from [<804717f0>] (dump_stack+0x20/0x24) [<804717f0>] (dump_stack+0x20/0x24) from [<80023cd0>] (warn_slowpath_common+0x5c/0x7c) [<80023cd0>] (warn_slowpath_common+0x5c/0x7c) from [<80023d1c>] (warn_slowpath_null+0x2c/0x34) [<80023d1c>] (warn_slowpath_null+0x2c/0x34) from [<8035ddb0>] (__clk_enable+0x34/0xb0) [<8035ddb0>] (__clk_enable+0x34/0xb0) from [<8035de54>] (clk_enable+0x28/0x3c) [<8035de54>] (clk_enable+0x28/0x3c) from [<8031a160>] (s3c_rtc_probe+0xf4/0x434) [<8031a160>] (s3c_rtc_probe+0xf4/0x434) from [<8028e288>] (platform_drv_probe+0x24/0x28) [<8028e288>] (platform_drv_probe+0x24/0x28) from [<8028ce10>] (driver_probe_device+0xbc/0x22c) [<8028ce10>] (driver_probe_device+0xbc/0x22c) from [<8028cff8>] (__driver_attach+0x78/0x9c) [<8028cff8>] (__driver_attach+0x78/0x9c) from [<8028bdfc>] (bus_for_each_dev+0x64/0xac) [<8028bdfc>] (bus_for_each_dev+0x64/0xac) from [<8028c7e0>] (driver_attach+0x28/0x30) [<8028c7e0>] (driver_attach+0x28/0x30) from [<8028c43c>] (bus_add_driver+0xe0/0x234) [<8028c43c>] (bus_add_driver+0xe0/0x234) from [<8028d55c>] (driver_register+0xac/0x13c) [<8028d55c>] (driver_register+0xac/0x13c) from [<8028e4f4>] (platform_driver_register+0x54/0x68) [<8028e4f4>] (platform_driver_register+0x54/0x68) from [<8065c944>] (s3c_rtc_driver_init+0x14/0x1c) [<8065c944>] (s3c_rtc_driver_init+0x14/0x1c) from [<800086d8>] (do_one_initcall+0x60/0x138) [<800086d8>] (do_one_initcall+0x60/0x138) from [<80633a8c>] (kernel_init_freeable+0x108/0x1d0) [<80633a8c>] (kernel_init_freeable+0x108/0x1d0) from [<8046d2f8>] (kernel_init+0x1c/0xf4) [<8046d2f8>] (kernel_init+0x1c/0xf4) from [<8000e358>] (ret_from_fork+0x14/0x20) ---[ end trace 4bcdc801c868d73f ]--- Signed-off-by:
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- Apr 25, 2013
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Stefano Stabellini authored
Signed-off-by:
Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by:
Marc Zyngier <marc.zyngier@arm.com> CC: rob.herring@calxeda.com CC: will.deacon@arm.com CC: arnd@arndb.de
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Stefano Stabellini authored
xenvm is based on mach-vexpress, move it to mach-virt. Changes in v4: - update the dts Makefile too. Signed-off-by: -
Thomas Abraham authored
Add chip-id controller nodes for Exynos4 and Exynos5 SoCs. Signed-off-by:
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- Apr 24, 2013
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Wenyou Yang authored
Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Tested-by:
Richard Genoud <richard.genoud@gmail.com> Signed-off-by:
Mark Brown <broonie@opensource.wolfsonmicro.com>
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Richard Genoud authored
Signed-off-by:
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Richard Genoud authored
Signed-off-by:
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- Apr 19, 2013
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Arnd Bergmann authored
The exynos combiner irqchip needs to find the parent interrupts and needs to know their number, so add the missing properties for exynos4 as they were already present for exynos5. Signed-off-by: -
Nicolas Ferre authored
"atmel,sama5ek" compatibility sting does not correspond to a useful board configuration. This d34ek.dts is the only sama5d3 .dts file affected. Reported-by:
Josh Wu <josh.wu@atmel.com> Signed-off-by:
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Ludovic Desroches authored
Add DMA resources to MCI nodes. Signed-off-by:
Ludovic Desroches <ludovic.desroches@atmel.com> [nicolas.ferre@atmel.com: correct 9g45, 9n12 dma phandle name] Signed-off-by:
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Ludovic Desroches authored
Add DMA resources to i2c nodes. Signed-off-by:
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- Apr 18, 2013
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Ludovic Desroches authored
Moving to generic DMA DT binding involves to set #dma-cells to 2. Signed-off-by:
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- Apr 17, 2013
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Manjunathappa, Prakash authored
Enable m25p64 SPI flash support on da850-EVM. Also add partition information of SPI flash. Signed-off-by:
Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com>
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Manjunathappa, Prakash authored
Patch adds SPI1 DT node along with pinmux data. Signed-off-by:
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- Apr 15, 2013
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Gregory CLEMENT authored
In order to be able to use more than 4GB of RAM when the LPAE is activated, the dts must be converted in 64 bits. Only Armada XP is LPAE capable, but as it shares a common dtsi file with Armada 370, then the common file include the skeleton64. Thanks to the use of the overload capability of the device tree format, armada-370 include the 32 bit skeleton and all the armada 370 based dts can remain the same. This was heavily based on the work of Lior Amsalem. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Gregory CLEMENT authored
Introduce a 'internal-regs' subnode, under which all devices are moved. This is not really needed for now, but will be for the mvebu-mbus driver. This generates a lot of code movement since it's indenting by one more tab all the devices. So it was a good opportunity to fix all the bad indentation. Signed-off-by:
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Gregory CLEMENT authored
This conversion will allow to keep 32 bits addresses for the internal registers whereas the memory of the system will be 64 bits. Later it will also ease the move of the mvebu-mbus driver to the device tree support. Signed-off-by:
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Thomas Petazzoni authored
reorganize the .dts and .dtsi files so that all devices are under the soc { } node (currently some devices such as the interrupt controller, the L2 cache and a few others are outside). Signed-off-by:Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Thomas Petazzoni authored
Align the cpu node indentation with the rest of the file [gc]: added a commit description Signed-off-by:
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Thomas Petazzoni authored
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
The Marvell evaluation board (DB) for the Armada 370 SoC has 2 physical full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
The Globalscale Mirabox platform uses one PCIe interface for an available mini-PCIe slot, and the other PCIe interface for an internal USB 3.0 controller. We add the necessary Device Tree informations to enable those two interfaces. Signed-off-by:
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Thomas Petazzoni authored
The Marvell evaluation board (DB) for the Armada XP SoC has 6 physicals full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can be used to plug mini-PCIe devices. We therefore enable the PCIe interface that corresponds to this slot. Signed-off-by:
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