Commits · 71a553cfa6325f82bf69d5626cdabd628ac05247 · jan.koester / Linux · GitLab

May 03, 2016
- Merge tag 'clk-renesas-for-v4.7-tag3' of... · 71a553cf
  Stephen Boyd authored May 02, 2016
  71a553cf
- Merge tag 'sunxi-clocks-for-4.7' of... · 51de8760
  Stephen Boyd authored May 02, 2016
  51de8760
May 02, 2016
- Merge tag 'tegra-for-4.7-clk' of... · 5bc75324
  Stephen Boyd authored May 02, 2016
  5bc75324
- Merge tag 'v4.7-rockchip-clk3' of... · 5569aedf
  Stephen Boyd authored May 02, 2016
  5569aedf
Apr 28, 2016
- clk: tegra: dfll: Reformat CVB frequency table · 2690e912
  Thierry Reding authored Apr 08, 2016
  2690e912
- clk: tegra: dfll: Properly clean up on failure and removal · f7c42d98
  Thierry Reding authored Apr 08, 2016
  f7c42d98
- clk: tegra: dfll: Make code more comprehensible · e8f6a68c
  Thierry Reding authored Apr 08, 2016
  e8f6a68c
- clk: tegra: dfll: Reference CVB table instead of copying data · 27ed2f7e
  Thierry Reding authored Apr 08, 2016
  27ed2f7e
- clk: tegra: dfll: Update kerneldoc · 8eaaae99
  Thierry Reding authored Apr 08, 2016
  8eaaae99
- clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 · 79709730
  Lucas Stach authored Feb 29, 2016
  79709730
- clk: tegra: Initialize PLL_C to sane rate on Tegra30 · a02cc84a
  Lucas Stach authored Feb 29, 2016
  a02cc84a
- clk: tegra: Fix pllre Tegra210 and add pll_re_out1 · 926655f9
  Rhyland Klein authored Mar 21, 2016
  926655f9
- clk: tegra: Add sor_safe clock · a91bb605
  Thierry Reding authored Apr 20, 2015
  a91bb605
- clk: tegra: dpaux and dpaux1 are fixed factor clocks · eede7113
  Thierry Reding authored Apr 20, 2015
  eede7113
- clk: tegra: Add dpaux1 clock · 98c4b366
  Thierry Reding authored Apr 20, 2015
  98c4b366
- clk: tegra: Use correct parent for dpaux clock · 3d0f4e5f
  Thierry Reding authored Apr 20, 2015
  3d0f4e5f
- clk: tegra: Add fixed factor peripheral clock type · 1ec7032a
  Thierry Reding authored Apr 20, 2015
  1ec7032a
- clk: tegra: Special-case mipi-cal parent on Tegra114 · 07314fc1
  Thierry Reding authored Apr 08, 2015
  07314fc1
- clk: tegra: Remove trailing blank line · a9caa848
  Thierry Reding authored Apr 20, 2015
  a9caa848
- clk: tegra: Constify peripheral clock registers · 7e14f223
  Thierry Reding authored Apr 20, 2015
  7e14f223
- clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs · 3358d2d9
  Andrew Bresticker authored Jun 18, 2015
  3358d2d9
- clk: renesas: cpg-mssr: Use always-on governor for Clock Domain · d04a75af
  Geert Uytterhoeven authored Apr 22, 2016
  d04a75af
- clk: renesas: cpg-mssr: Postpone call to pm_genpd_init() · 93662500
  Geert Uytterhoeven authored Apr 22, 2016
  93662500
- clk: renesas: mstp: Use always-on governor for Clock Domain · 20729300
  Geert Uytterhoeven authored Apr 22, 2016
  20729300
- clk: renesas: mstp: Postpone call to pm_genpd_init() · b3a52d75
  Geert Uytterhoeven authored Apr 22, 2016
  b3a52d75
Apr 26, 2016
- clk: renesas: r8a7795: Add VIN clocks · ccce262d
  Niklas Söderlund authored Apr 25, 2016
  ccce262d
- clk: renesas: r8a7795: Add CSI2 clocks · 0187d321
  Niklas Söderlund authored Apr 25, 2016
  0187d321
Apr 25, 2016
- clk: rockchip: fix the rk3399 cifout clock · fd8bc829
  Xing Zheng authored Apr 20, 2016
  fd8bc829
- clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399 · 50961e83
  Xing Zheng authored Apr 20, 2016
  50961e83
- clk: rockchip: add some frequencies on the rk3399 PLL table · aa2897ce
  Xing Zheng authored Apr 20, 2016
  aa2897ce
- clk: rockchip: assign more necessary rk3399 clock ids · 3f92a054
  Xing Zheng authored Apr 20, 2016
  3f92a054
- Merge branch 'v4.7-shared/clkids' into v4.7-clk/next · de87985e
  Heiko Stuebner authored Apr 25, 2016
  
  de87985e
- clk: rockchip: export some necessary rk3399 clock ids · 55df4584
  Xing Zheng authored Apr 20, 2016
  55df4584
- clk: rockchip: rename rga clock-id on rk3399 · 003e6eb7
  Xing Zheng authored Apr 20, 2016
  003e6eb7
- clk: rockchip: add general gpu soft-reset on rk3399 · f73b5042
  Xing Zheng authored Apr 20, 2016
  f73b5042
- clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399 · f3d40914
  Xing Zheng authored Apr 20, 2016
  f3d40914
- clk: sunxi: Let divs clocks read the base factor clock name from devicetree · ff2bb893
  Jens Kuske authored Mar 18, 2016
  ff2bb893
- clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type · b8199ff3
  Colin Ian King authored Apr 24, 2016
  b8199ff3
Apr 21, 2016
- clk: sunxi: Add TCON channel1 clock · cc510c73
  Maxime Ripard authored Jul 01, 2015
  cc510c73
- clk: sunxi: Add PLL3 clock · fa4d0ca1
  Maxime Ripard authored Mar 23, 2016
  fa4d0ca1